-
公开(公告)号：FR2586517B1
公开(公告)日：1991-11-22
申请号：FR8611964
申请日：1986-08-21
Applicant: RCA CORP
Inventor： BESSLER ROGER FRANK , ARBEITER JAMES HENRY , SINNIGER JOSEPH OWEN
IPC: H04N5/21 , G06F15/00 , G06F17/10 , G06K9/54 , G06T1/00 , G08C13/00 , H03H17/00 , H03H17/02 , H04N7/26 , H04N7/54 , H03M7/30 , G01R23/167 , H04N5/14
Abstract: The amount of hardware required to implement a Burt Pyramid or an FSD (filter-subtract-decimate) pyramid analyzer (or synthesizer) stage of a sampled temporal signal representing an n-dimensional information component or (such as a video signal) is substantially reduced by employing a time-synchronized multiplexed analyzer stage to derive (or a time-synchronized multiplexed synthesizer stage that is responsive to) a single serial stream of samples of a predetermined plural number of sub-spectra that are arranged in a predetermined temporal order format with respect to one another in accordance with each of a given set of time synchronized, repetitively generated, serially applied control signals.
-
公开(公告)号：GB2144603B
公开(公告)日：1986-10-15
申请号：GB8419693
申请日：1984-08-02
Applicant: RCA CORP
Inventor： SINNIGER JOSEPH OWEN , PETERSON RICHARD MATEER
Abstract: A multiplex bus system comprises a master control unit (MCU) connected to at least one receiver-transmit unit (RTU) by a data bus. The MCU transmits to the RTU a message comprising a synchronization pulse of known duration and successive time spaced timing signals separated by time duration T marking the boundaries of data bits to be transmitted from the RTU to the MCU. The RTU includes a clock pulse source which utilizes the synchronization pulse to determine the frequency of the clock pulse source in P pulses per duration T. The value P is used in conjunction with the timing signals to create properly timed data determining signals in the data bits.
-
公开(公告)号：IT8121939D0
公开(公告)日：1981-05-25
申请号：IT2193981
申请日：1981-05-25
Applicant: RCA CORP
Inventor： SINNIGER JOSEPH OWEN , ROBBI ANTHONY DREA
-
公开(公告)号：GB2179818A
公开(公告)日：1987-03-11
申请号：GB8620142
申请日：1986-08-19
Applicant: RCA CORP
Inventor： BESSLER ROGER FRANK , ARBEITER JAMES HENRY , SINNIGER JOSEPH OWEN
IPC: H04N5/21 , G06F15/00 , G06F17/10 , G06K9/54 , G06T1/00 , G08C13/00 , H03H17/00 , H03H17/02 , H04N7/26 , H04N7/54 , G01R23/16
Abstract: The amount of hardware required to implement a Burt Pyramid or an FSD (filter-subtract-decimate) pyramid analyzer (or synthesizer) stage of a sampled temporal signal representing an n-dimensional information component or (such as a video signal) is substantially reduced by employing a time-synchronized multiplexed analyzer stage to derive (or a time-synchronized multiplexed synthesizer stage that is responsive to) a single serial stream of samples of a predetermined plural number of sub-spectra that are arranged in a predetermined temporal order format with respect to one another in accordance with each of a given set of time synchronized, repetitively generated, serially applied control signals.
-
公开(公告)号：DE3428588A1
公开(公告)日：1985-02-21
申请号：DE3428588
申请日：1984-08-02
Applicant: RCA CORP
Inventor： SINNIGER JOSEPH OWEN , PETERSON RICHARD MATEER
Abstract: A multiplex bus system comprises a master control unit (MCU) connected to at least one receiver-transmit unit (RTU) by a data bus. The MCU transmits to the RTU a message comprising a synchronization pulse of known duration and successive time spaced timing signals separated by time duration T marking the boundaries of data bits to be transmitted from the RTU to the MCU. The RTU includes a clock pulse source which utilizes the synchronization pulse to determine the frequency of the clock pulse source in P pulses per duration T. The value P is used in conjunction with the timing signals to create properly timed data determining signals in the data bits.
-
Patent Agency Ranking
公开(公告)号：GB2179818B
公开(公告)日：1989-08-09
申请号：GB8620142
申请日：1986-08-19
Applicant: RCA CORP
Inventor： BESSLER ROGER FRANK , ARBEITER JAMES HENRY , SINNIGER JOSEPH OWEN
IPC: H04N5/21 , G06F15/00 , G06F17/10 , G06K9/54 , G06T1/00 , G08C13/00 , H03H17/00 , H03H17/02 , H04N7/26 , H04N7/54
Abstract: The amount of hardware required to implement a Burt Pyramid or an FSD (filter-subtract-decimate) pyramid analyzer (or synthesizer) stage of a sampled temporal signal representing an n-dimensional information component or (such as a video signal) is substantially reduced by employing a time-synchronized multiplexed analyzer stage to derive (or a time-synchronized multiplexed synthesizer stage that is responsive to) a single serial stream of samples of a predetermined plural number of sub-spectra that are arranged in a predetermined temporal order format with respect to one another in accordance with each of a given set of time synchronized, repetitively generated, serially applied control signals.
-
公开(公告)号：DE3628349A1
公开(公告)日：1987-03-05
申请号：DE3628349
申请日：1986-08-21
Applicant: RCA CORP
Inventor： BESSLER ROGER FRANK , ARBEITER JAMES HENRY , SINNIGER JOSEPH OWEN
IPC: H04N5/21 , G06F15/00 , G06F17/10 , G06K9/54 , G06T1/00 , G08C13/00 , H03H17/00 , H03H17/02 , H04N7/26 , H04N7/54 , G06F15/62 , G06F7/00
Abstract: The amount of hardware required to implement a Burt Pyramid or an FSD (filter-subtract-decimate) pyramid analyzer (or synthesizer) stage of a sampled temporal signal representing an n-dimensional information component or (such as a video signal) is substantially reduced by employing a time-synchronized multiplexed analyzer stage to derive (or a time-synchronized multiplexed synthesizer stage that is responsive to) a single serial stream of samples of a predetermined plural number of sub-spectra that are arranged in a predetermined temporal order format with respect to one another in accordance with each of a given set of time synchronized, repetitively generated, serially applied control signals.
-
公开(公告)号：FR2586517A1
公开(公告)日：1987-02-27
申请号：FR8611964
申请日：1986-08-21
Applicant: RCA CORP
Inventor： BESSLER ROGER FRANK , ARBEITER JAMES HENRY , SINNIGER JOSEPH OWEN
IPC: H04N5/21 , G06F15/00 , G06F17/10 , G06K9/54 , G06T1/00 , G08C13/00 , H03H17/00 , H03H17/02 , H04N7/26 , H04N7/54 , H03M7/30 , G01R23/167 , H04N5/14
Abstract: The amount of hardware required to implement a Burt Pyramid or an FSD (filter-subtract-decimate) pyramid analyzer (or synthesizer) stage of a sampled temporal signal representing an n-dimensional information component or (such as a video signal) is substantially reduced by employing a time-synchronized multiplexed analyzer stage to derive (or a time-synchronized multiplexed synthesizer stage that is responsive to) a single serial stream of samples of a predetermined plural number of sub-spectra that are arranged in a predetermined temporal order format with respect to one another in accordance with each of a given set of time synchronized, repetitively generated, serially applied control signals.
-
公开(公告)号：GB2144603A
公开(公告)日：1985-03-06
申请号：GB8419693
申请日：1984-08-02
Applicant: RCA CORP
Inventor： SINNIGER JOSEPH OWEN , PETERSON RICHARD MATEER
Abstract: A multiplex bus system comprises a master control unit (MCU) connected to at least one receiver-transmit unit (RTU) by a data bus. The MCU transmits to the RTU a message comprising a synchronization pulse of known duration and successive time spaced timing signals separated by time duration T marking the boundaries of data bits to be transmitted from the RTU to the MCU. The RTU includes a clock pulse source which utilizes the synchronization pulse to determine the frequency of the clock pulse source in P pulses per duration T. The value P is used in conjunction with the timing signals to create properly timed data determining signals in the data bits.
-
公开(公告)号：FR2485101B1
公开(公告)日：1986-11-28
申请号：FR8112164
申请日：1981-06-19
Applicant: RCA CORP
Inventor： SINNIGER JOSEPH OWEN , ROBBI ANTHONY DREA
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.02 seconds)
