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    Chrominance signal correction
    3.
    发明授权
    Chrominance signal correction 失效

    公开(公告)号：US3873990A

    公开(公告)日：1975-03-25

    申请号：US39362673

    申请日：1973-08-31

    Applicant: RCA CORP

    Inventor： WILBER JAMES ALBERT

    IPC: H04N9/45 ,  H04N9/85 ,  H04N5/76

    CPC classification number: H04N9/85

    Abstract: In a video disc player, a recorded composite signal, recovered during disc playback, includes a chrominance signal component buried in the midband of the accompanying luminance signal component. The player includes video processing circuits converting the recovered signal to an output composite signal in which the chrominance signal component occupies a higher frequency band, and employing the step of heterodyning the recovered chrominance signal with oscillations at a nominal frequency of fs + fs'' (where fs is the color subcarrier frequency of the output, and fs'' is the buried color subcarrier frequency of the disc signal). To stabilize the output chrominance signal component against spurious frequency variations accompanying disc playback, a phase locked loop (PLL) system is established to cause the fs + fs'' oscillations to track the disc frequency variations. The PLL system employs a voltage controlled oscillator (VCO) operating at a nominal frequency of fs + fs'', and responding to the output of a phase detector, comparing the synchronizing burst component of the output chrominance signal with the highly stable output of a reference oscillator operating at fs. The recorded synchronizing burst component includes bursts of conventional short duration following each horizontal sync pulse but additionally includes an elongated burst component (of the same subcarrier frequency and phase) occupying a line interval during the ''''backporch'''' portion of the vertical blanking interval. The PLL system phase detector is supplied with both short and elongated burst components through use of appropriate line rate and field rate gating of the output chrominance signal. Presence of elongated burst component in the phase detector input substantially precludes ''''sidelock'''' condition (i.e., PLL system locking to a sideband component of the color synchronizing waveform under turn-on conditions when turntable speed is incorrect, and maintaining such a locked state as speed is corrected).

    Chrominance signal correction
    4.
    发明授权
    Chrominance signal correction 失效
    色度信号校正

    公开(公告)号：US3871020A

    公开(公告)日：1975-03-11

    申请号：US35756473

    申请日：1973-05-07

    Applicant: RCA CORP

    Inventor： WILBER JAMES ALBERT

    IPC: H04N9/85 ,  H04N9/02 ,  H04N5/76

    CPC classification number: H04N9/85

    Abstract: In a video disc player, a recorded composite signal, recovered during disc playback, includes a chrominance signal component buried in the midband of the accompanying luminance signal component. The player includes video processing circuits converting the recovered signal to an output composite signal in which the chrominance signal component occupies a higher frequency band, and employing the step of heterodyning the recovered composite signal with oscillations at a nominal frequency of fs + fs'' (where fs is the color subcarrier frequency of the output, and fs'' is the buried color subcarrier frequency of the disc signal). To stabilize the output chrominance signal component against spurious frequency variations accompanying disc playback, a phase locked loop (PLL) system is established to cause the fs + fs'' oscillations to track the disc frequency variations. The PLL system employs a voltage controlled oscillator (VCO) operating at a nominal frequency of 1/2 fs fs'', and responding to the output of a phase detector, comparing the synchronizing burst component of the output chrominance signal with the highly stable output of a reference oscillator operating at fs. The VCO output is heterodyned with oscillations at 3/2 fs, derived from the reference oscillator, to provide the desired oscillation output varying about fs + fs''. ''''Sidelock'''' under disc playback initiation conditions is avoided by limiting the hold-in range of the VCO. A sweep voltage input to the VCO is supplied under out-of-lock conditions to enable phase lock acquisition. Upon achievement of phase lock, sweep generation is disabled, and sweep voltage sweeps back to mid-range value with normal slope. Sample-and-hold circuitry is employed in error voltage development, to enable PLL system to hold within rapid pull-in range during lengthy signal dropouts.

    Abstract translation: 在视频光盘播放机中，在光盘播放期间恢复的记录复合信号包括掩埋在伴随的亮度信号分量的中间带中的色度信号分量。 播放器包括将恢复信号转换为色度信号分量占据较高频带的输出复合信号的视频处理电路，并采用将恢复的复合信号以标称频率fs + fs'进行外差的步调（其中 fs是输出的彩色副载波频率，fs'是盘信号的掩埋彩色副载波频率）。 为了稳定输出色度信号分量，防止伴随光盘播放的杂散频率变化，建立了锁相环（PLL）系统，以使fs + fs的振荡跟踪光盘的频率变化。 PLL系统采用以1/2 fs - fs'的标称频率工作的压控振荡器（VCO），并响应相位检测器的输出，将输出色度信号的同步脉冲串分量与高度稳定的输出进行比较 的参考振荡器以fs运行。 VCO输出通过从基准振荡器得到的3/2 fs的振荡进行外差，以提供关于fs + fs'变化的期望振荡输出。 通过限制VCO的保持范围来避免光盘播放启动条件下的“Sidelock”。 在锁定状态下提供输入到VCO的扫频电压，以实现锁相采集。 实现相位锁定时，禁止扫描生成，扫描电压以正常斜率扫描回到中间值。 采样保持电路用于误差电压开发，以便在冗长的信号丢失期间使PLL系统能够在快速拉入范围内保持。

    5.
    发明专利
    未知

    公开(公告)号：IT1132347B

    公开(公告)日：1986-07-02

    申请号：IT2405080

    申请日：1980-08-07

    Applicant: RCA CORP

    Inventor： TODD CHRISTOPHER J ,  WILBER JAMES ALBERT

    IPC: G11B9/06 ,  H04N5/903 ,  G11B19/28 ,  G11B21/02 ,  G11B21/03 ,  H04N9/85 ,  H04N9/89 ,  G11B

    Abstract: Periodic biasing of video disc player signal correction servo to the center of its control range avoids the loss-of-loop gain which otherwise could occur if the servo were continuously biased and minimizes loop stabilization time. Periodic biasing is provided by means of a timing circuit, responsive to a luminance signal transition above blanking level, which enables the servo phase error detector and simultaneously enables a precharging circuit which charges the servo error voltage holding capacitor to a level corresponding to a zero error servo condition. The timing circuit disables the precharging circuit a predetermined time subsequent to an opposite transition of the luminance signal and disables the phase detector subsequent to disabling of the precharging circuit. The period between disabling of the precharging circuit and disabling of the phase detector encompasses the color burst interval of the horizontal sync pulse and may be controlled by selection of offset and slope parameters of an integrator in the timing circuit.

    8.
    发明专利
    未知

    公开(公告)号：DE3031466A1

    公开(公告)日：1981-03-26

    申请号：DE3031466

    申请日：1980-08-20

    Applicant: RCA CORP

    Inventor： PYLES GERALD DEE ,  WILBER JAMES ALBERT ,  CHRISTOPHER TODD J

    IPC: G11B3/00 ,  G11B7/00 ,  G11B7/004 ,  G11B9/06 ,  G11B20/02 ,  G11B21/03 ,  G11B27/36 ,  H04B1/10 ,  H04N5/93 ,  H04N5/781

    Abstract: A squelch circuit responsive to a squelch signal mutes audio and video circuits in a video disc player, preconditions a video signal correction servo system to the center of its control range and inhibits a defect correction circuit. A squelch memory, set by the simultaneous occurrence of the squelch signal and a loss of carrier signal derived from the output of the player pickup transducer, maintains the muting, preconditioning and inhibiting functions. When the squelch signal terminates the squelch memory is reset upon subsequent termination of the loss of carrier signal whereby the audio and video circuits are immediately unmuted, stabilization is rapidly established by the preconditioned video signal correction servo system and the defect correction circuit is primed.

    9.
    发明专利
    未知

    公开(公告)号：FR2464004A1

    公开(公告)日：1981-02-27

    申请号：FR8018153

    申请日：1980-08-19

    Applicant: RCA CORP

    Inventor： PYLES GERALD DEE ,  WILBER JAMES ALBERT ,  CHRISTOPHER TODD J

    IPC: G11B3/00 ,  G11B7/00 ,  G11B7/004 ,  G11B9/06 ,  G11B20/02 ,  G11B21/03 ,  G11B27/36 ,  H04B1/10 ,  H04N5/93 ,  H04N5/91

    Abstract: A squelch circuit responsive to a squelch signal mutes audio and video circuits in a video disc player, preconditions a video signal correction servo system to the center of its control range and inhibits a defect correction circuit. A squelch memory, set by the simultaneous occurrence of the squelch signal and a loss of carrier signal derived from the output of the player pickup transducer, maintains the muting, preconditioning and inhibiting functions. When the squelch signal terminates the squelch memory is reset upon subsequent termination of the loss of carrier signal whereby the audio and video circuits are immediately unmuted, stabilization is rapidly established by the preconditioned video signal correction servo system and the defect correction circuit is primed.

    10.
    发明专利
    未知

    公开(公告)号：FR2464002A1

    公开(公告)日：1981-02-27

    申请号：FR8018152

    申请日：1980-08-19

    Applicant: RCA CORP

    Inventor： CHRISTOPHER TODD J ,  WILBER JAMES ALBERT

    IPC: H04N5/903 ,  G11B9/06 ,  G11B19/28 ,  G11B21/02 ,  G11B21/03 ,  H04N9/85 ,  H04N9/89 ,  H04N5/76

    Abstract: Periodic biasing of video disc player signal correction servo to the center of its control range avoids the loss-of-loop gain which otherwise could occur if the servo were continuously biased and minimizes loop stabilization time. Periodic biasing is provided by means of a timing circuit, responsive to a luminance signal transition above blanking level, which enables the servo phase error detector and simultaneously enables a precharging circuit which charges the servo error voltage holding capacitor to a level corresponding to a zero error servo condition. The timing circuit disables the precharging circuit a predetermined time subsequent to an opposite transition of the luminance signal and disables the phase detector subsequent to disabling of the precharging circuit. The period between disabling of the precharging circuit and disabling of the phase detector encompasses the color burst interval of the horizontal sync pulse and may be controlled by selection of offset and slope parameters of an integrator in the timing circuit.

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