公开(公告)号：DE10196328T1

公开(公告)日：2003-08-28

申请号：DE10196328

申请日：2001-06-06

Applicant: ROSEMOUNT INC

Inventor： ANDERSON STEPHEN D ,  HULSE DANIEL V ,  MOORE KEVIN B ,  KAMMANN PAUL D ,  MAALOUF GABRIEL A

IPC: H04L27/00 ,  H04L27/14 ,  H04L27/22 ,  H04L27/227 ,  H04L27/233 ,  H03D3/00

Abstract: A receiver receives modulated message signals in non-coherent FSK and coherent 8PSK protocols. A selectively configurable processor demodulates the message signals, and includes a demodulator that derives in-phase and quadrature signals based on the message signals. A phase detector is responsive to the in-phase and quadrature signals and delayed in-phase and quadrature signals to derive a phase signal. A selector is responsive to the in-phase and quadrature signals to selectively connect a loop filter between the phase detector and the demodulator. When the selector connects the filter between the phase detector and demodulator, the demodulator is responsive to filtered phase signals to lock onto a frequency of the message signals so that the processor operates as a phase locked loop to demodulate coherent modulated signals. When the selector disconnects the filter from between the phase detector and the demodulator, the demodulator demodulates non-coherent modulated signals and the phase detector supplies a phase signal representing the slope of the phase of the demodulated signal.

公开(公告)号：WO0195478A3

公开(公告)日：2002-06-13

申请号：PCT/US0140856

申请日：2001-06-06

Applicant: ROSEMOUNT INC

Inventor： ANDERSON STEPHEN D ,  HULSE DANIEL V ,  MOORE KEVIN B ,  KAMMANN PAUL D ,  MAALOUF GABRIEL A

IPC: H04L27/00 ,  H04L27/14 ,  H04L27/22 ,  H04L27/227 ,  H04L27/233

CPC classification number: H04L27/2331 ,  H04L27/2273 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0079

Abstract: A receiver (FIG. 3) receives FSK and coherent 8PSK protocols. A selectively configurable processor (20) demodulates the message signals, and includes a demodulator (50-58) that derives in-phase and quadrature signals based on the message signals. A phase detector (60-64) is responsive to the in-phase and quadrature signals and delayed in-phase and quadrature signals to derive a phase signal. A selector (26) is responsive to the in-phase and quadrature signals to selectively connect a loop filter (66) between the phase detector and the demodulator. When the selector (26) connects the filter (66) between the phase detector (60-64) and demodulator (50-58), the demodulator is responsive to filtered phase signals to lock onto a frequency of the message signals so that the processor (20) operates as a phase locked loop to demodulate coherent modulated signals. When the selector (26) disconnects the filter (66) from between the phase detector (60-64) and the demodulator (50-58), the demodulator demodulates non-coherent modulated signals and the phase detector supplies a phase signal representing the slope of the phase of the demodulated signal.

Abstract translation: 接收机（图3）接收FSK和相干8PSK协议。 可选择性地配置的处理器（20）对消息信号进行解调，并且包括基于消息信号导出同相和正交信号的解调器（50-58）。 相位检测器（60-64）响应于同相和正交信号以及延迟的同相和正交信号以导出相位信号。 选择器（26）响应于同相和正交信号以选择性地连接相位检测器和解调器之间的环路滤波器（66）。 当选择器（26）连接相位检测器（60-64）和解调器（50-58）之间的滤波器（66）时，解调器响应于滤波的相位信号来锁定消息信号的频率，使得处理器 （20）作为锁相环来解调相干调制信号。 当选择器（26）将相位检测器（60-64）和解调器（50-58）之间的滤波器（66）断开时，解调器解调非相干调制信号，相位检测器提供表示斜率的相位信号 的解调信号的相位。

公开(公告)号：AU6703001A

公开(公告)日：2001-12-17

申请号：AU6703001

申请日：2001-06-06

Applicant: ROSEMOUNT INC

Inventor： ANDERSON STEPHEN D ,  HULSE DANIEL V ,  MOORE KEVIN B ,  KAMMANN PAUL D ,  MAALOUF GABRIEL A

IPC: H04L27/00 ,  H04L27/14 ,  H04L27/22 ,  H04L27/227 ,  H04L27/233

Abstract: A receiver receives modulated message signals in non-coherent FSK and coherent 8PSK protocols. A selectively configurable processor demodulates the message signals, and includes a demodulator that derives in-phase and quadrature signals based on the message signals. A phase detector is responsive to the in-phase and quadrature signals and delayed in-phase and quadrature signals to derive a phase signal. A selector is responsive to the in-phase and quadrature signals to selectively connect a loop filter between the phase detector and the demodulator. When the selector connects the filter between the phase detector and demodulator, the demodulator is responsive to filtered phase signals to lock onto a frequency of the message signals so that the processor operates as a phase locked loop to demodulate coherent modulated signals. When the selector disconnects the filter from between the phase detector and the demodulator, the demodulator demodulates non-coherent modulated signals and the phase detector supplies a phase signal representing the slope of the phase of the demodulated signal.