公开(公告)号：BR9206536A

公开(公告)日：1995-10-24

申请号：BR9206536

申请日：1992-08-20

Applicant: ROSEMOUNT INC

Inventor： ANDERSON STEPHEN D ,  FRICK ROGER L ,  MONZO GLEN E ,  WESTFIELD BRIAN L

IPC: G08C19/02 ,  G08C19/00

Abstract: A three wire transmitter bidirectionally communicates AC signals to and from a first external device and sends DC signals to a second external device. The transmitter includes a communication circuit which is energized from power and common terminals and includes memory storage for transmitter status and a process variable (PV). The communication circuit receives a sensor output indicative of the PV and provides the DC signal and the AC signal to a signal terminal which connects to both external devices, and also receives AC signals from the first external device. The communications circuit has a characteristic AC impedance between the signal and common terminals over an AC frequency range for receiving and transmitting AC signals to and from the first external device so that the receiving signals are not shorted out and so the transmitted signals can be received. The communications circuit has a characteristic DC impedance between the signal and common terminals over a range of frequencies which include DC and typically extend to approximately 20 Hz. The characteristic impedance is substantially lower than the impedance of the second external device which receives DC signals so that the accuracy of the DC signal is not compromised.

公开(公告)号：CA2119438A1

公开(公告)日：1993-04-01

申请号：CA2119438

申请日：1992-08-20

Applicant: ROSEMOUNT INC

Inventor： ANDERSON STEPHEN D ,  FRICK ROGER L ,  MONZO GLEN E ,  WESTFIELD BRIAN L

IPC: G08C19/02 ,  G08C19/00

Abstract: A three wire transmitter bidirectionally communicates AC signals to and from a first external device and sends DC signals to a second external device. The transmitter includes a sensor circuit and a communication circuit, both energized from power and common terminals of the transmitter. The communication circuit receives a sensor output indicating a sensed process variable and provide DC and AC signals to a signal terminal which connects to both external devices, and also receives AC signals from the first external device. The DC signal is representative of the sensed process variable and the AC signal is digitally representative of the sensed process variable and of transmitter data selected by the received AC signal.

公开(公告)号：WO0195478A3

公开(公告)日：2002-06-13

申请号：PCT/US0140856

申请日：2001-06-06

Applicant: ROSEMOUNT INC

Inventor： ANDERSON STEPHEN D ,  HULSE DANIEL V ,  MOORE KEVIN B ,  KAMMANN PAUL D ,  MAALOUF GABRIEL A

IPC: H04L27/00 ,  H04L27/14 ,  H04L27/22 ,  H04L27/227 ,  H04L27/233

CPC classification number: H04L27/2331 ,  H04L27/2273 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0079

Abstract: A receiver (FIG. 3) receives FSK and coherent 8PSK protocols. A selectively configurable processor (20) demodulates the message signals, and includes a demodulator (50-58) that derives in-phase and quadrature signals based on the message signals. A phase detector (60-64) is responsive to the in-phase and quadrature signals and delayed in-phase and quadrature signals to derive a phase signal. A selector (26) is responsive to the in-phase and quadrature signals to selectively connect a loop filter (66) between the phase detector and the demodulator. When the selector (26) connects the filter (66) between the phase detector (60-64) and demodulator (50-58), the demodulator is responsive to filtered phase signals to lock onto a frequency of the message signals so that the processor (20) operates as a phase locked loop to demodulate coherent modulated signals. When the selector (26) disconnects the filter (66) from between the phase detector (60-64) and the demodulator (50-58), the demodulator demodulates non-coherent modulated signals and the phase detector supplies a phase signal representing the slope of the phase of the demodulated signal.

Abstract translation: 接收机（图3）接收FSK和相干8PSK协议。 可选择性地配置的处理器（20）对消息信号进行解调，并且包括基于消息信号导出同相和正交信号的解调器（50-58）。 相位检测器（60-64）响应于同相和正交信号以及延迟的同相和正交信号以导出相位信号。 选择器（26）响应于同相和正交信号以选择性地连接相位检测器和解调器之间的环路滤波器（66）。 当选择器（26）连接相位检测器（60-64）和解调器（50-58）之间的滤波器（66）时，解调器响应于滤波的相位信号来锁定消息信号的频率，使得处理器 （20）作为锁相环来解调相干调制信号。 当选择器（26）将相位检测器（60-64）和解调器（50-58）之间的滤波器（66）断开时，解调器解调非相干调制信号，相位检测器提供表示斜率的相位信号 的解调信号的相位。

公开(公告)号：DE10196328T1

公开(公告)日：2003-08-28

申请号：DE10196328

申请日：2001-06-06

Applicant: ROSEMOUNT INC

Inventor： ANDERSON STEPHEN D ,  HULSE DANIEL V ,  MOORE KEVIN B ,  KAMMANN PAUL D ,  MAALOUF GABRIEL A

IPC: H04L27/00 ,  H04L27/14 ,  H04L27/22 ,  H04L27/227 ,  H04L27/233 ,  H03D3/00

Abstract: A receiver receives modulated message signals in non-coherent FSK and coherent 8PSK protocols. A selectively configurable processor demodulates the message signals, and includes a demodulator that derives in-phase and quadrature signals based on the message signals. A phase detector is responsive to the in-phase and quadrature signals and delayed in-phase and quadrature signals to derive a phase signal. A selector is responsive to the in-phase and quadrature signals to selectively connect a loop filter between the phase detector and the demodulator. When the selector connects the filter between the phase detector and demodulator, the demodulator is responsive to filtered phase signals to lock onto a frequency of the message signals so that the processor operates as a phase locked loop to demodulate coherent modulated signals. When the selector disconnects the filter from between the phase detector and the demodulator, the demodulator demodulates non-coherent modulated signals and the phase detector supplies a phase signal representing the slope of the phase of the demodulated signal.

公开(公告)号：CA2222548A1

公开(公告)日：1996-12-19

申请号：CA2222548

申请日：1996-05-31

Applicant: ROSEMOUNT INC

Inventor： PIECHOWSKI TODD A ,  LOUWAGIE BENNETT L ,  ANDERSON STEPHEN D ,  WESTFIELD BRIAN L

IPC: G05B11/36 ,  G05B19/042 ,  G05B19/418 ,  H04L25/02 ,  G08C19/16

Abstract: Conversion circuitry (40) for use in a process control system (10) is adapted for coupling to a primary process control loop (26). Digital receiver circuitry (46, 52) in the conversion circuitry (40) receives a digital signal transmitted over the primary process control loop (26) from a field transmitter (22) and responsively provides a digital output. A microprocessor (50) receives the digital output and responsively provides a secondary loop control output. Secondary loop control circuitry (62) for coupling to a secondary process control loop (58) receives the secondary loop control output from the microprocessor (50) and responsively controls current flowing through the secondary process control loop (58). The current flowing through the secondary process control loop (58) is related to the digital signal transmitted by the field transmitter (22).

公开(公告)号：AU667682B2

公开(公告)日：1996-04-04

申请号：AU2543492

申请日：1992-08-20

Applicant: ROSEMOUNT INC

Inventor： ANDERSON STEPHEN D ,  FRICK ROGER L ,  MONZO GLEN E ,  WESTFIELD BRIAN L

IPC: G08C19/02 ,  H04B3/02 ,  G08C19/00

Abstract: A three wire transmitter bidirectionally communicates AC signals to and from a first external device and sends DC signals to a second external device. The transmitter includes a communication circuit which is energized from power and common terminals and includes memory storage for transmitter status and a process variable (PV). The communication circuit receives a sensor output indicative of the PV and provides the DC signal and the AC signal to a signal terminal which connects to both external devices, and also receives AC signals from the first external device. The communications circuit has a characteristic AC impedance between the signal and common terminals over an AC frequency range for receiving and transmitting AC signals to and from the first external device so that the receiving signals are not shorted out and so the transmitted signals can be received. The communications circuit has a characteristic DC impedance between the signal and common terminals over a range of frequencies which include DC and typically extend to approximately 20 Hz. The characteristic impedance is substantially lower than the impedance of the second external device which receives DC signals so that the accuracy of the DC signal is not compromised.

公开(公告)号：AU6703001A

公开(公告)日：2001-12-17

申请号：AU6703001

申请日：2001-06-06

Applicant: ROSEMOUNT INC

Inventor： ANDERSON STEPHEN D ,  HULSE DANIEL V ,  MOORE KEVIN B ,  KAMMANN PAUL D ,  MAALOUF GABRIEL A

IPC: H04L27/00 ,  H04L27/14 ,  H04L27/22 ,  H04L27/227 ,  H04L27/233

Abstract: A receiver receives modulated message signals in non-coherent FSK and coherent 8PSK protocols. A selectively configurable processor demodulates the message signals, and includes a demodulator that derives in-phase and quadrature signals based on the message signals. A phase detector is responsive to the in-phase and quadrature signals and delayed in-phase and quadrature signals to derive a phase signal. A selector is responsive to the in-phase and quadrature signals to selectively connect a loop filter between the phase detector and the demodulator. When the selector connects the filter between the phase detector and demodulator, the demodulator is responsive to filtered phase signals to lock onto a frequency of the message signals so that the processor operates as a phase locked loop to demodulate coherent modulated signals. When the selector disconnects the filter from between the phase detector and the demodulator, the demodulator demodulates non-coherent modulated signals and the phase detector supplies a phase signal representing the slope of the phase of the demodulated signal.

公开(公告)号：BR9609144A

公开(公告)日：1999-02-17

申请号：BR9609144

申请日：1996-05-31

Applicant: ROSEMOUNT INC

Inventor： ANDERSON STEPHEN D ,  WESTFIELD BRIAN L ,  LOUWAGIE BENNETT L ,  PIECHOWSKI TODD A

IPC: G05B11/36 ,  G05B19/042 ,  G05B19/418 ,  H04L25/02

公开(公告)号：CA2238495A1

公开(公告)日：1998-04-02

申请号：CA2238495

申请日：1997-09-17

Applicant: ROSEMOUNT INC

Inventor： ANDERSON STEPHEN D ,  TETZLAFF DAVID E ,  SCHNAARE THEODORE H ,  JUNK BRIAN S ,  ORMAN MICHAEL A ,  JOHNSON THEODORE L

IPC: G08C19/02 ,  H02M7/219 ,  G05B11/01 ,  G08C19/00

Abstract: A field instrument (10) includes an input circuit (26) having a transistor bridge rectifier (Q1, Q2, Q3, Q4) which is couplable to a power supply. The transistor bridge rectifier (Q1, Q2, Q3, Q4) is configured to provide power from the power supply to a remainder of the field instrument (10).

公开(公告)号：DE69222652D1

公开(公告)日：1997-11-13

申请号：DE69222652

申请日：1992-08-20

Applicant: ROSEMOUNT INC

Inventor： ANDERSON STEPHEN D ,  FRICK ROGER ,  MONZO GLEN ,  WESTFIELD BRIAN

IPC: G08C19/02 ,  G08C19/00

Abstract: A three wire transmitter bidirectionally communicates AC signals to and from a first external device and sends DC signals to a second external device. The transmitter includes a communication circuit which is energized from power and common terminals and includes memory storage for transmitter status and a process variable (PV). The communication circuit receives a sensor output indicative of the PV and provides the DC signal and the AC signal to a signal terminal which connects to both external devices, and also receives AC signals from the first external device. The communications circuit has a characteristic AC impedance between the signal and common terminals over an AC frequency range for receiving and transmitting AC signals to and from the first external device so that the receiving signals are not shorted out and so the transmitted signals can be received. The communications circuit has a characteristic DC impedance between the signal and common terminals over a range of frequencies which include DC and typically extend to approximately 20 Hz. The characteristic impedance is substantially lower than the impedance of the second external device which receives DC signals so that the accuracy of the DC signal is not compromised.