公开(公告)号：US20040235241A1

公开(公告)日：2004-11-25

申请号：US10793867

申请日：2004-03-08

Applicant: Renesas Technology Corp.

Inventor： Masatoshi Anma ,  Masahiko Takeuchi

IPC: H01L021/8242

CPC classification number: H01L28/91 ,  H01L21/31683 ,  H01L27/10852 ,  H01L28/65

Abstract: It is an object to obtain a method of manufacturing a semiconductor device having a capacitor capable of avoiding generation of a leakage current and an electrical short circuit between electrodes which are caused by a sharp portion of a lower electrode of the capacitor and a deterioration in a crystallinity of a dielectric film of the capacitor which is caused by a residue. A surface of a ruthenium film (7) is oxidized by a low temperature plasma oxidation process to form a ruthenium oxide film (9). Also in the case in which a part of a residue (51) exists on the surface of the ruthenium film (7), the existing residue (51) is lifted off and disappears by formation of the ruthenium oxide film (9) containing RuO4 having a high vapor pressure in a large amount. The low temperature plasma oxidation process, moreover, has an anisotropy an oxidation rate in a vertical direction is higher than that in a transverse direction. Accordingly, an upper end of a side wall portion of the ruthenium film (7) is greatly oxidized in the vertical direction and is thus rounded. As a result, a sharp portion (50) disappears.

Abstract translation: 本发明的目的是获得一种具有电容器的半导体器件的制造方法，所述电容器能够避免由电容器的下部电极的尖锐部分引起的漏电流和电极之间的电短路以及电容器的劣化 由残留物引起的电容器的电介质膜的结晶度。 钌膜（7）的表面通过低温等离子体氧化法氧化，形成氧化钌膜（9）。 此外，在钌膜（7）的表面存在一部分残留物（51）的情况下，通过形成含有RuO 4的氧化钌膜（9），使现有的残渣（51）脱落而消失，所述RuO 4具有 大量蒸气压高。 此外，低温等离子体氧化法具有各向异性，垂直方向的氧化速度高于横向的氧化速度。 因此，钌膜（7）的侧壁部的上端在垂直方向上被大大氧化，因此是圆形的。 结果，尖锐部分（50）消失。

公开(公告)号：US20040089891A1

公开(公告)日：2004-05-13

申请号：US10658425

申请日：2003-09-10

Applicant: Renesas Technology Corp.

Inventor： Masatoshi Anma ,  Masahiko Takeuchi

IPC: H01L027/108 ,  H01L029/76 ,  H01L029/94 ,  H01L031/119

CPC classification number: H01L27/10852 ,  H01L23/5226 ,  H01L23/53252 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A lower electrode (11) formed of ruthenium has an opening generated by a void at time of formation, for example. A ruthenium oxide film (14) is provided on an upper surface of the lower electrode (11) to close an entry of the opening, and is formed by oxidizing the lower electrode (11). Similarly, a ruthenium oxide film (841) is provided to close an entry of an opening of a plug body (81) formed of ruthenium.

Abstract translation: 例如，由钌形成的下部电极（11）在形成时具有由空隙产生的开口。 氧化钌膜（14）设置在下电极（11）的上表面上，以封闭开口的入口，并且通过氧化下电极（11）形成氧化钌膜。 类似地，提供氧化钌膜（841）以闭合由钌形成的塞体（81）的开口的入口。

公开(公告)号：US20040232462A1

公开(公告)日：2004-11-25

申请号：US10697316

申请日：2003-10-31

Applicant: Renesas Technology Corp.

Inventor： Masahiko Takeuchi

IPC: H01L021/8242 ,  H01L027/108 ,  H01L029/76 ,  H01L031/119

CPC classification number: H01L28/65 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/105 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).

Abstract translation: 即使在形成电容器的电介质膜时进行氧化，也能够实现存储元件的接触电阻的降低和逻辑元件的接触电阻的降低的技术。 导电阻挡层（82）设置在电连接到源极/漏极区域（59）的接触插塞（83b）的顶端。 电容器（73）的下电极（70）形成为与接触塞（83b）的导电阻挡层（82）接触，然后电容器（73）的电介质膜（71）和上电极（72）依次 形成。 在逻辑区域中，接触插塞（25）形成在上层中，使得它们分别与电源/漏极区域（9）电连接的接触插塞（33）接触。

公开(公告)号：US20040152297A1

公开(公告)日：2004-08-05

申请号：US10623512

申请日：2003-07-22

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Kenichi Ooto ,  Masahiko Takeuchi ,  Yoshinori Tanaka

IPC: H01L021/4763

CPC classification number: H01L21/76897

Abstract: A method of manufacturing a semiconductor device includes the steps of: forming an interlayer insulating film covering an upper side of a projected gate portion and a gap between the projected gate portions; forming a contact hole reaching a first bottom portion introduced into a semiconductor substrate, from an upper surface of the interlayer insulating film through the gap between the projected gate portions; forming a second bottom portion having the semiconductor substrate exposed on the bottom face and the side face by forming a diffusion prevention film covering a side face of the first bottom portion and by etching further the bottom face of the first bottom portion; and forming a plug by filling the contact hole with polysilicon having an impurity doped.

Abstract translation: 制造半导体器件的方法包括以下步骤：形成覆盖突出的栅极部分的上侧和突出的栅极部分之间的间隙的层间绝缘膜; 通过所述突出的栅极部之间的间隙从所述层间绝缘膜的上表面形成到达引入到半导体衬底中的第一底部的接触孔; 通过形成覆盖所述第一底部的侧面的扩散防止膜，并进一步蚀刻所述第一底部的底面，形成具有在所述底面和所述侧面上露出的所述半导体衬底的第二底部; 以及通过用具有掺杂杂质的多晶硅填充接触孔来形成插塞。

公开(公告)号：US20040108534A1

公开(公告)日：2004-06-10

申请号：US10455325

申请日：2003-06-06

Applicant: Renesas Technology Corp.

Inventor： Takaaki Tsunomura ,  Masahiko Takeuchi

IPC: H01L027/108

CPC classification number: H01L28/65 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91

Abstract: A storage node in a capacitor of a semiconductor device is formed of: an inner conductor in a columnar form having bottom, side and top surfaces; and an outer conductor, located on the bottom (between the bottom surface and the semiconductor substrate), side and top surfaces of the inner conductor, having a different material from that of the inner conductor. The outer conductor is formed of a metal film such as of Ru having a film thickness of about 40 nm to 80 nm. The inner conductor is formed of a film, such as a TiN film, a TaN film, a WN film or the like, having a high adhesion to the metal film such as of Ru. With this configuration, it is possible to provide a semiconductor device provided with a capacitor of which the capacitance is obtained.

Abstract translation: 半导体器件的电容器中的存储节点由具有底部，侧面和顶部表面的柱状形式的内部导体形成; 以及位于底部（底面和半导体衬底之间），内部导体的侧表面和顶表面之间的外部导体，其具有与内部导体不同的材料。 外导体由膜厚为约40nm至80nm的诸如Ru的金属膜形成。 内部导体由诸如RuN的金属膜具有高粘附性的诸如TiN膜，TaN膜，WN膜等的膜形成。 利用这种配置，可以提供一种设置有获得电容的电容器的半导体器件。