公开(公告)号：US20040169228A1

公开(公告)日：2004-09-02

申请号：US10619431

申请日：2003-07-16

Applicant: Renesas Technology Corp.

Inventor： Motoi Ashida ,  Takashi Terada

IPC: H01L027/01

CPC classification number: H01L21/76897 ,  H01L21/76895 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with a CMOS transistor structure in which a gate electrode and a wire connecting an Nnull-type active region and a Pnull-type active region overlap each other in plan view, to reduce a footprint of the CMOS transistor structure, is provided. An Nnull-type active region (1) of an n-channel MOS transistor and a Pnull-type active region (2) of a p-channel MOS transistor are formed in a surface portion of a semiconductor substrate by ion implantation or the like. Gate electrodes (3) are formed on the Nnull-type active region (1) and the Pnull-type active region (2). Insulating films (4, 5) of silicon nitride are formed on the gate electrodes (3). An interlayer insulating film (6) of silicon oxide is formed over the gate electrodes (3) covered with the insulating films (4, 5), by CVD or the like. Openings (7) for accommodating wires connecting the Nnull-type active region (1) and the Pnull-type active region (2) are formed in the interlayer insulating film (6). A metal film such as an aluminum film is buried in the openings (7), to form buried wires (8).

Abstract translation: 具有CMOS晶体管结构的半导体器件，其中栅极电极和连接N +型有源区和P +型有源区的导线在平面图中彼此重叠，以减少CMOS的占空比 晶体管结构。 在沟道MOS晶体管的n沟道MOS晶体管和P +型有源区（2）中的N +型有源区（1）形成在半导体衬底的表面部分 离子注入等。 栅电极（3）形成在N +型有源区（1）和P +型有源区（2）上。 在栅电极（3）上形成氮化硅绝缘膜（4,5）。 通过CVD等在绝缘膜（4,5）覆盖的栅电极（3）上形成氧化硅层间绝缘膜（6）。 用于容纳连接N +型有源区（1）和P +型有源区（2）的导线的开口（7）形成在层间绝缘膜（6）中。 将诸如铝膜的金属膜掩埋在开口（7）中，以形成掩埋线（8）。

公开(公告)号：US20040097064A1

公开(公告)日：2004-05-20

申请号：US10435046

申请日：2003-05-12

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Takashi Terada ,  Motoi Ashida ,  Tomohiro Hosokawa ,  Yasuichi Masuda

IPC: H01L021/00 ,  H01L021/4763

CPC classification number: H01L21/76897 ,  H01L21/76895

Abstract: As an opening exposing a surface of an element-forming region positioned in a region lying between two gate electrodes, a first opening is formed based on a resist pattern formed such that a portion of a region where the opening is formed overlaps two-dimensionally with a portion of one gate electrode. As an opening exposing a surface of one gate electrode, a second opening is formed based on a resist pattern formed such that a region where the opening is formed overlaps two-dimensionally solely with one gate electrode. Here, the first opening is covered with a non-photosensitive, organic film and the resist pattern. Thereafter, a tungsten interconnection is formed in the first and second openings. Thus, a semiconductor device, of which production cost is reduced, and in which electrical short-circuit and falling off of an interconnection are suppressed, can be obtained.

Abstract translation: 作为露出位于两个栅极之间的区域中的元件形成区域的表面的开口，基于抗蚀剂图案形成第一开口，该抗蚀剂图案形成为使得形成开口的区域的一部分与二维地重叠二维地与 一个栅电极的一部分。 作为露出一个栅电极的表面的开口，基于形成为使得形成开口的区域仅用一个栅电极二维重叠的区域形成第二开口。 这里，第一开口被非光敏有机膜和抗蚀剂图案覆盖。 此后，在第一和第二开口中形成钨互连。 因此，可以获得抑制生产成本降低并且互连的电短路和掉电的半导体器件。

公开(公告)号：US20040227162A1

公开(公告)日：2004-11-18

申请号：US10724618

申请日：2003-12-02

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Motoi Ashida

IPC: H01L027/10

CPC classification number: H01L21/823835 ,  H01L21/76897 ,  H01L21/823842 ,  H01L21/823871

Abstract: A semiconductor device includes: a semiconductor substrate having two types of active regions that are a PMOS region and an NMOS region separated from each other in plan view by a PN separation film; and a dual-gate electrode extending linearly across the PMOS region, the PN separation film and the NMOS region collectively on an upper side of the semiconductor substrate. The dual-gate electrode includes a P-type portion, an N-type portion and a PN junction positioned therebetween. The PN junction includes a silicide region. The silicide region is apart from both the PMOS region and the NMOS region and formed within the area of the PN separation film in plan view.

Abstract translation: 半导体器件包括：半导体衬底，其具有两个类型的有源区，PMOS区和NMOS平面在平面图中由PN分离膜分离; 以及双重栅极电极，其在PMOS区域上线性延伸，PN分离膜和NMOS区域共同在半导体衬底的上侧。 双栅极电极包括P型部分，N型部分和位于它们之间的PN结。 PN结包括硅化物区域。 硅化物区域与PMOS区域和NMOS区域分开，并且在平面图中形成在PN分离膜的区域内。

公开(公告)号：US20040222451A1

公开(公告)日：2004-11-11

申请号：US10801657

申请日：2004-03-17

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Motoi Ashida

IPC: H01L027/108

CPC classification number: G11C11/412 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

Abstract: An access transistor, provided between a storage node in a memory cell and a bit line is formed of a P channel MOS transistor including P type first and second impurity regions formed in an N type well and a gate electrode. Buried interconnection is formed of metal having high melting point such as tungsten and provided stacked on a driver transistor formed on a main surface of a P type well and the access transistor. A polysilicon film forming a P channel TFT as a load element is formed on the buried interconnection, which is planarized, with an interlayer insulating film interposed.

Abstract translation: 设置在存储单元中的存储节点和位线之间的存取晶体管由包括形成在N型阱和栅电极中的P型第一和第二杂质区的P沟道MOS晶体管形成。 掩埋互连由诸如钨的高熔点金属形成，并且被堆叠在形成在P型阱的主表面上的驱动晶体管和存取晶体管上。 形成作为负载元件的P沟道TFT的多晶硅膜被形成在被平坦化的掩埋互连上，并夹有层间绝缘膜。