公开(公告)号：EP2065893A1

公开(公告)日：2009-06-03

申请号：EP08253714.3

申请日：2008-11-13

Applicant: Renesas Technology Corp.

Inventor： Kajiyama, Shinya ,  Shinagawa, Yutaka ,  Mizuno, Makoto ,  Kasai, Hideo ,  Watanabe, Takao ,  Takemura, Riichiro ,  Sekiguchi, Tomonori

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1075 ,  G11C16/26

Abstract: The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.

Abstract translation: 半导体集成电路装置包括：第一锁存器，其可以保持X解码器的输出信号，并且在X解码器之后的后级将信号传送到字驱动器; 第二锁存器，其可以保持Y解码器的输出信号，并且在Y解码器之后的后级中将信号传送到列多路复用器; 以及第三锁存器，其可以保持读出放大器的输出信号，并且在读出放大器之后的后级中将该信号传送到输出缓冲器。 该结构使得可以管理一系列用于读取存储在非易失性半导体存储器中的数据的处理，并且即使在来自CPU的访问请求冲突的情况下也能够进行低延迟访问。