公开(公告)号：US20040196695A1

公开(公告)日：2004-10-07

申请号：US10805365

申请日：2004-03-22

Applicant: Renesas Technology Corp.

Inventor： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

IPC: G11C011/34

CPC classification number: G11C16/10 ,  G11C16/0433

Abstract: Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 iA to flow a current in the memory cell.

Abstract translation: 这里公开了一种通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入并降低功耗的方法。 当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。 此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。 并且，在恒定电流源晶体管中流动约1IA的恒定电流，并且通过约1iA的恒定电流放电位线以使存储单元中的电流流动。

公开(公告)号：US20040202020A1

公开(公告)日：2004-10-14

申请号：US10810672

申请日：2004-03-29

Applicant: Renesas Technology Corp.

Inventor： Masamichi Fujito ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Ayako Kakuda ,  Akira Kato ,  Toshihiro Tanaka

IPC: G11C015/00

CPC classification number: G11C7/18 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/26 ,  G11C16/28 ,  G11C16/30 ,  G11C2207/005 ,  G11C2216/22

Abstract: The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.

Abstract translation: 能够进行电气重写的片上非易失性存储器的读取速度增加。 非易失性存储器具有分层位线结构，其具有对多个存储器阵列中的每一个特定的第一位线，在多个存储器阵列之间共享的第二位线，第一选择器电路，用于为每个存储器阵列选择第一位线 将所选择的第一位线连接到第二位线，以及布置在第一选择器电路的输出和第二位线之间的感测放大器。 具有划分的存储器阵列的层次位线结构可以减小感测放大器的输入负载能力。

公开(公告)号：US20040207025A1

公开(公告)日：2004-10-21

申请号：US10811902

申请日：2004-03-30

Applicant: Renesas Technology Corp.

Inventor： Shoichiro Chiba ,  Koji Okumura ,  Toshihiro Tanaka

IPC: G11C011/34

CPC classification number: G11C16/0425 ,  G11C16/0466 ,  H01L29/40114 ,  H01L29/40117

Abstract: The invention provides a data processor realizing high-speed reading of an on-chip nonvolatile memory and improvement in defect repairing efficiency. For a nonvolatile memory, nonvolatile memory cells each having a split-gate structure including a memory transistor part of an ONO structure and a selection transistor part for selecting the memory transistor part are employed. The gate withstand voltage of the selection transistor part can be lower than that of the memory transistor part, so that it is convenient to increase reading speed. A specific storage region which can be read by a resetting instruction of the data processor is assigned to a storage region in the nonvolatile memory, and repair information and the like is stored in the specific storage region. An internal circuit to which the repair information is transferred replaces a normal storage region instructed by the repair information with a redundant storage region. Thus, a program for an electric fuse and a laser fuse is not required to designate an object to be repaired.

Abstract translation: 本发明提供了实现片上非易失性存储器的高速读取并提高缺陷修复效率的数据处理器。 对于非易失性存储器，采用各自具有包括ONO结构的存储晶体管部分和用于选择存储晶体管部分的选择晶体管部分的分离栅极结构的非易失性存储器单元。 选择晶体管部分的栅极耐受电压可以低于存储晶体管部分的栅极耐受电压，从而提高读取速度是方便的。 可以通过数据处理器的复位指令读取的特定存储区域被分配给非易失性存储器中的存储区域，并且修复信息等被存储在特定存储区域中。 传输修复信息的内部电路用冗余存储区域代替由维修信息指示的正常存储区域。 因此，不需要用于电熔丝和激光熔丝的程序来指定要修复的对象。