公开(公告)号：EP3796561A1

公开(公告)日：2021-03-24

申请号：EP20193565.7

申请日：2020-08-31

Applicant: RichWave Technology Corp.

Inventor： Chien, Hwey-Ching ,  Chen, Chih-Sheng ,  Lin, Jhao-Yi ,  Hsu, Ching-Wen

IPC: H04B1/18

Abstract: The frequency detector (100) includes a first impedance circuit (110) and a second impedance circuit (120). The first impedance circuit (110) has a first terminal for receiving an input signal (SIG IN ), and a second terminal for outputting a divisional signal (SIG DVS ). The second impedance circuit (120) has a first terminal coupled to the second terminal of the first impedance circuit (110), and a second terminal coupled to a first system voltage terminal (NV1). The frequency response of the first impedance circuit (110) is different from a frequency response of the second impedance circuit (120). The resistance of the first impedance circuit (110), a resistance of the second impedance circuit (120), and the divisional signal (SIG DVS ) change with a frequency of the input signal (SIG IN ).

公开(公告)号：EP3709510A3

公开(公告)日：2020-11-04

申请号：EP19217298.9

申请日：2019-12-18

Applicant: RichWave Technology Corp.

Inventor： Chien, Hwey-Ching

IPC: H03G7/00 ,  H03G7/06

Abstract: A power detector (10, 10B) has a signal input terminal (Pin), N limiting amplifiers (30A, 30B, 30C, 30D), N rectifiers (40A, 40B, 40C, 40D) and a signal output end. N is an integer greater than 1. The signal input terminal receives an input signal (Si), and the signal output end outputs a detection signal (VPD). The N limiting amplifiers generate N amplified signals (Vop1, Vop2, Vop3, Vop4) according to N attenuated signals (Vinp1, Vinp2, Vinp3, Vinp4) having different attenuation. Each rectifier (40A, 40B, 40C, 40D) receives a corresponding amplified signal and outputs a rectified signal. The detection signal (VPD) is associated with the sum of N rectified signals (Io1, Io2, Io3, Io4) outputted from the N rectifiers (40A, 40B, 40C, 40D), and all transistors of the power detector (10, 10B) are bipolar junction transistors.

公开(公告)号：EP3709510A2

公开(公告)日：2020-09-16

申请号：EP19217298.9

申请日：2019-12-18

Applicant: RichWave Technology Corp.

Inventor： Chien, Hwey-Ching

IPC: H03G7/00 ,  H03G7/06

Abstract: A power detector (10, 10B) has a signal input terminal (Pin), N limiting amplifiers (30A, 30B, 30C, 30D), N rectifiers (40A, 40B, 40C, 40D) and a signal output end. N is an integer greater than 1. The signal input terminal receives an input signal (Si), and the signal output end outputs a detection signal (VPD). The N limiting amplifiers generate N amplified signals (Vop1, Vop2, Vop3, Vop4) according to N attenuated signals (Vinp1, Vinp2, Vinp3, Vinp4) having different attenuation. Each rectifier (40A, 40B, 40C, 40D) receives a corresponding amplified signal and outputs a rectified signal. The detection signal (VPD) is associated with the sum of N rectified signals (Io1, Io2, Io3, Io4) outputted from the N rectifiers (40A, 40B, 40C, 40D), and all transistors of the power detector (10, 10B) are bipolar junction transistors.