公开(公告)号：US20240312923A1

公开(公告)日：2024-09-19

申请号：US18677075

申请日：2024-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji SONG ,  Byeongchan KIM ,  Jumyong PARK ,  Jinho AN ,  Chungsun LEE ,  Jeonggi JIN ,  Juil CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

公开(公告)号：US20230238316A1

公开(公告)日：2023-07-27

申请号：US18189834

申请日：2023-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Chungsun LEE ,  Teahwa JEONG ,  Jeonggi JIN

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L25/0652

Abstract: A method for manufacturing a semiconductor package may include: forming a photoimageable dielectric layer on a substrate including a pad; forming a preliminary via hole in the photoimageable dielectric layer to expose the pad; forming a hard mask layer on the photoimageable dielectric layer and the pad; etching the photoimageable dielectric layer and the hard mask layer to form a via hole, a first hole, and a trench; forming a metal layer on the photoimageable dielectric layer connected to the pad; planarizing the metal layer to form a wiring pattern; and placing a semiconductor chip electrically connected to the wiring pattern. The first hole may be disposed on the via hole and connected thereto, and a diameter of the first hole may be larger than a diameter of the via hole.

公开(公告)号：US20220059466A1

公开(公告)日：2022-02-24

申请号：US17198359

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji SONG ,  Byeongchan KIM ,  Jumyong PARK ,  Jinho AN ,  Chungsun LEE ,  Jeonggi JIN ,  Juil CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

公开(公告)号：US20210384137A1

公开(公告)日：2021-12-09

申请号：US17147661

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-IL CHOI ,  Gyuho KANG ,  Seong-Hoon BAE ,  Dongjoon OH ,  Chungsun LEE ,  Hyunsu HWANG

IPC: H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48

Abstract: A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.

公开(公告)号：US20240312894A1

公开(公告)日：2024-09-19

申请号：US18668974

申请日：2024-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Chungsun LEE ,  Jeonggi JIN ,  Jinho CHUN

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49822

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

公开(公告)号：US20230112006A1

公开(公告)日：2023-04-13

申请号：US17826521

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoon OH ,  Unbyoung KANG ,  Byeongchan KIM ,  Jumyong PARK ,  Solji SONG ,  Chungsun LEE ,  Hyunsu HWANG

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes: a first semiconductor chip including a first semiconductor substrate including a first active surface and a first inactive surface opposite to each other and a plurality of first chip pads on the first active surface; a second semiconductor chip including a second semiconductor substrate including a second active surface and a second inactive surface opposite to each other and a plurality of second chip pads on the second active surface, the second active surface being stacked on the first semiconductor chip to face the first inactive surface; a bonding insulation material layer interposed between the first semiconductor chip and the second semiconductor chip; and a plurality of bonding pads surrounded by the bonding insulation material layer to electrically connect the first semiconductor chip to the second semiconductor chip.

公开(公告)号：US20230070532A1

公开(公告)日：2023-03-09

申请号：US17726363

申请日：2022-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong PARK ,  Unbyoung KANG ,  Byeongchan KIM ,  Solji SONG ,  Chungsun LEE

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

公开(公告)号：US20220037248A1

公开(公告)日：2022-02-03

申请号：US17364558

申请日：2021-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Chungsun LEE ,  Jeonggi JIN ,  Jinho CHUN

IPC: H01L23/498

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

公开(公告)号：US20240421012A1

公开(公告)日：2024-12-19

申请号：US18210134

申请日：2023-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangsick PARK ,  Chungsun LEE ,  Hanmin LEE ,  Seungyoon JUNG

IPC: H01L23/24 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device includes a first semiconductor chip having a first through silicon via (TSV). A second semiconductor chip is arranged on the first semiconductor chip and includes a second TSV positioned on a same vertical line as the first TSV. A conductive pad is disposed on each of the first TSV and the second TSV. The conductive pad electrically connects the first semiconductor chip and the second semiconductor chip to each other. A warpage prevention metal structure is disposed on an upper surface of the first semiconductor chip or an upper surface of the second semiconductor chip.

公开(公告)号：US20240157481A1

公开(公告)日：2024-05-16

申请号：US18233486

申请日：2023-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YEONGKWON KO ,  Soyeon KWON ,  Chungsun LEE ,  Jihun JUNG

IPC: B23K26/38 ,  B23K26/40 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/683

CPC classification number: B23K26/38 ,  B23K26/40 ,  H01L21/3043 ,  H01L21/3065 ,  H01L21/6836 ,  B23K2101/40

Abstract: A semiconductor chip splitting method using a laser includes: performing a back-end-of-line (BEOL) process comprising forming wiring at or above a front surface of a semiconductor substrate; forming a lower trench at a rear surface of the semiconductor substrate; forming a laser scribing line on the semiconductor substrate along a region overlapping the lower trench; and splitting the semiconductor substrate into chips by a process comprising cutting along the laser scribing line.