公开(公告)号：US20220059442A1

公开(公告)日：2022-02-24

申请号：US17230511

申请日：2021-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoon OH ,  Junyun KWEON ,  Jumyong PARK ,  Jin Ho AN ,  Chungsun LEE ,  Hyunsu HWANG

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538

Abstract: Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.

公开(公告)号：US20150270221A1

公开(公告)日：2015-09-24

申请号：US14729264

申请日：2015-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Ho AN ,  Byung Lyul PARK ,  Soyoung LEE ,  Gilheyun CHOI

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/09 ,  H01L2224/0401 ,  H01L2224/08146 ,  H01L2224/13 ,  H01L2224/16145 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: Semiconductor devices, and methods of fabricating a semiconductor device, include forming a via hole through a first surface of a substrate, the via hole being spaced apart from a second surface facing the first surface, forming a first conductive pattern in the via hole, forming an insulating pad layer on the first surface of the substrate, the insulating pad having an opening exposing the first conductive pattern, performing a thermal treatment on the first conductive pattern to form a protrusion protruding from a top surface of the first conductive pattern toward the opening, and then, forming a second conductive pattern in the opening.

Abstract translation: 半导体器件以及制造半导体器件的方法包括：通过基板的第一表面形成通孔，所述通孔与面向第一表面的第二表面间隔开，在通孔中形成第一导电图案，形成 在所述基板的第一表面上的绝缘垫层，所述绝缘垫具有暴露所述第一导电图案的开口，对所述第一导电图案进行热处理，以形成从所述第一导电图案的顶表面朝向所述开口突出的突起 ，然后在开口中形成第二导电图案。

公开(公告)号：US20140162449A1

公开(公告)日：2014-06-12

申请号：US14094963

申请日：2013-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Ho AN ,  Byung-Lyul PARK ,  Soyoung LEE ,  Gilheyun CHOI

IPC: H01L21/768

CPC classification number: H01L23/5384 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/09 ,  H01L2224/0401 ,  H01L2224/08146 ,  H01L2224/13 ,  H01L2224/16145 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: Semiconductor devices, and methods of fabricating a semiconductor device, include forming a via hole through a first surface of a substrate, the via hole being spaced apart from a second surface facing the first surface, forming a first conductive pattern in the via hole, forming an insulating pad layer on the first surface of the substrate, the insulating pad having an opening exposing the first conductive pattern, performing a thermal treatment on the first conductive pattern to form a protrusion protruding from a top surface of the first conductive pattern toward the opening, and then, forming a second conductive pattern in the opening.

Abstract translation: 半导体器件以及制造半导体器件的方法包括：通过基板的第一表面形成通孔，所述通孔与面向第一表面的第二表面间隔开，在通孔中形成第一导电图案，形成 在所述基板的第一表面上的绝缘垫层，所述绝缘垫具有暴露所述第一导电图案的开口，对所述第一导电图案进行热处理，以形成从所述第一导电图案的顶表面朝向所述开口突出的突起 ，然后在开口中形成第二导电图案。

公开(公告)号：US20230238316A1

公开(公告)日：2023-07-27

申请号：US18189834

申请日：2023-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Chungsun LEE ,  Teahwa JEONG ,  Jeonggi JIN

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L25/0652

Abstract: A method for manufacturing a semiconductor package may include: forming a photoimageable dielectric layer on a substrate including a pad; forming a preliminary via hole in the photoimageable dielectric layer to expose the pad; forming a hard mask layer on the photoimageable dielectric layer and the pad; etching the photoimageable dielectric layer and the hard mask layer to form a via hole, a first hole, and a trench; forming a metal layer on the photoimageable dielectric layer connected to the pad; planarizing the metal layer to form a wiring pattern; and placing a semiconductor chip electrically connected to the wiring pattern. The first hole may be disposed on the via hole and connected thereto, and a diameter of the first hole may be larger than a diameter of the via hole.

公开(公告)号：US20220020714A1

公开(公告)日：2022-01-20

申请号：US17204313

申请日：2021-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Heewon KIM ,  Junyoung PARK ,  Seong-Hoon BAE ,  Jin Ho AN

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/538

Abstract: A semiconductor package device may include a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, which includes including a body portion and a protruding portion extended from the body portion to form a single object, an insulating layer covering a side surface of the body portion, and an outer coupling terminal on the protruding portion. The body portion may have a first diameter in a first direction parallel to the top surface of the redistribution substrate, and the protruding portion may have a second diameter in the first direction, which is smaller than the first diameter. A top surface of the protruding portion may be parallel to the first direction, and a side surface of the protruding portion may be inclined at an angle to a top surface of the body portion.

公开(公告)号：US20210233879A1

公开(公告)日：2021-07-29

申请号：US17229023

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il CHOI ,  Kwangjin MOON ,  Sujeong PARK ,  JuBin SEO ,  Jin Ho AN ,  Dong-chan LIM ,  Atsushi FUJISAKI

IPC: H01L23/00

Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

公开(公告)号：US20240290702A1

公开(公告)日：2024-08-29

申请号：US18655879

申请日：2024-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoon OH ,  Junyun KWEON ,  Jumyong PARK ,  Jin Ho AN ,  Chungsun LEE ,  Hyunsu HWANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227

Abstract: Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.

公开(公告)号：US20180053797A1

公开(公告)日：2018-02-22

申请号：US15630063

申请日：2017-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin LEE ,  Kwangjin MOON ,  Seokho KIM ,  Sukchul BANG ,  Jin Ho AN ,  Naein LEE

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14683 ,  H01L2224/11

Abstract: A semiconductor device includes a semiconductor substrate with first and second surfaces facing each other, an etch stop pattern in a trench formed in the first surface of the semiconductor substrate, a first insulating layer on the first surface of the semiconductor substrate, and a through via penetrating the semiconductor substrate and the first insulating layer. The etch stop pattern surrounds a portion of a lateral surface of the through via.

公开(公告)号：US20170200675A1

公开(公告)日：2017-07-13

申请号：US15403480

申请日：2017-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokyoung JUNG ,  Kwangjin MOON ,  Byung Lyul PARK ,  Jin Ho AN

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76826 ,  H01L21/76886 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2225/06544 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor devices including a through via structure and methods of forming the same are provided. The semiconductor devices may include a semiconductor substrate including a first surface and a second surface opposite the first surface, a front insulating layer on the first surface of the semiconductor substrate, a back insulating layer on the second surface of the semiconductor substrate, a through via structure extending through the back insulating layer, the semiconductor substrate, and the front insulating layer, a via insulating layer on a side surface of the through via structure, and a contact structure extending through the front insulating layer. The through via structure may include a first region and a second region disposed on the first region. The second region may include a first doping element, and the first region may be substantially free of the first doping element.

公开(公告)号：US20240429189A1

公开(公告)日：2024-12-26

申请号：US18822646

申请日：2024-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Heewon KIM ,  Junyoung PARK ,  Seong-Hoon BAE ,  Jin Ho AN

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/538

Abstract: A semiconductor package device may include a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, which includes including a body portion and a protruding portion extended from the body portion to form a single object, an insulating layer covering a side surface of the body portion, and an outer coupling terminal on the protruding portion. The body portion may have a first diameter in a first direction parallel to the top surface of the redistribution substrate, and the protruding portion may have a second diameter in the first direction, which is smaller than the first diameter. A top surface of the protruding portion may be parallel to the first direction, and a side surface of the protruding portion may be inclined at an angle to a top surface of the body portion.