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    7.
    发明专利
    未知

    公开(公告)号：DE60040107D1

    公开(公告)日：2008-10-09

    申请号：DE60040107

    申请日：2000-01-21

    Applicant: SEIKO EPSON CORP

    Inventor： HASEGAWA KAZUMASA ,  SHIMODA TATSUYA

    IPC: B41J2/045 ,  G09G3/34 ,  B06B1/06 ,  G02F1/167 ,  H01L27/20 ,  H01L41/09 ,  H01L41/107

    Abstract: A thin film piezoelectric transducer comprises a first electrode layer (24), piezoelectric film layer (25), second electrode layer (26), and third electrode layer (27) formed on a supporting base (22) wherein a cavity (21) is formed. The second electrode layer (26) and the third electrode layer (27) are formed in a pair with a space therebetween on the piezoelectric film layer (25) located above said cavity (21).

    FERROELECTRIC MEMORY DEVICE AND ITS MANUFACTURING METHOD, AND HYBRID DEVICE
    9.
    发明公开
    FERROELECTRIC MEMORY DEVICE AND ITS MANUFACTURING METHOD, AND HYBRID DEVICE 有权
    混合动物园中的FERROELEKTRISCHE SPEICHERANORDNUNG UND IHRE HERSTELLUNGSMETHODE UND HYBRID-ANORDNUNG

    公开(公告)号：EP1263048A4

    公开(公告)日：2005-04-27

    申请号：EP01956992

    申请日：2001-08-21

    Applicant: SEIKO EPSON CORP

    Inventor： HASEGAWA KAZUMASA ,  NATORI EIJI ,  NISHIKAWA TAKAO ,  OGUCHI KOICHI ,  SHIMODA TATSUYA

    IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115

    CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L27/11585 ,  H01L27/1159

    Abstract: A ferroelectric memory device comprises a memory cell array (100) including memory cells arranged in a matrix, first signal electrodes (12), second signal electrodes (16) arranged perpendicularly to the first electrodes (12), and a ferroelectric layer (14) disposed at least in an intersection of the first and second signal electrodes (12, 16) and a peripheral circuit (200) for selectively writing/reading information in/from the memory cell. The layer where the memory cell array (100) is provided is different from that where the peripheral circuit (200) is provided. The peripheral circuit (200) is provided in a region outside the memory cell array (100).

    Abstract translation: 本发明的铁电体存储器件包括存储单元阵列，其中存储单元布置在具有第一信号电极的矩阵中，沿与第一信号电极相交的方向排列的第二信号电极和至少设置在交叉区域中的铁电层 在第一信号电极和第二信号电极之间，以及用于选择性地将信息写入或从存储单元读取信息的外围电路部分。 存储单元阵列和外围电路部分形成在不同的层中。 外围电路部分形成在存储单元阵列外部的区域中。

    MEMORY CELL ARRAY WITH FERROELECTRIC CAPACITOR, METHOD FOR MANUFACTURING THE SAME, AND FERROELECTRIC MEMORY DEVICE
    10.
    发明公开
    MEMORY CELL ARRAY WITH FERROELECTRIC CAPACITOR, METHOD FOR MANUFACTURING THE SAME, AND FERROELECTRIC MEMORY DEVICE 审中-公开
    辣椒精油

    公开(公告)号：EP1263049A4

    公开(公告)日：2005-08-31

    申请号：EP01958382

    申请日：2001-08-21

    Applicant: SEIKO EPSON CORP

    Inventor： NATORI EIJI ,  HASEGAWA KAZUMASA ,  OGUCHI KOICHI ,  NISHIKAWA TAKAO ,  SHIMODA TATSUYA

    IPC: H01L27/105 ,  G11C11/22 ,  H01L21/02 ,  H01L21/8246 ,  H01L27/10 ,  H01L21/033 ,  H01L21/316 ,  H01L27/08

    CPC classification number: H01L28/55 ,  G11C11/22 ,  H01L27/101

    Abstract: A memory cell array where a ferroelectric layer constituting a ferroelectric capacitor has a specific pattern and the stray capacitance of a signal electrode is small, a method for manufacturing the memory cell array, and a ferroelectric memory device. The memory cell array (100A) has memory cells each consisting of a ferroelectric capacitor (20) and arranged in a matrix. The ferroelectric capacitor (20) has a first signal electrode (12), a second signal electrode (16) arranged in a direction perpendicular to the first signal electrode (12), and a ferroelectric layer (14) linearly arranged along the first signal electrode (12) or the second signal electrode (16). The ferroelectric layer (14) can be arranged alternatively in a block only in the intersection of the first signal electrode (12) and the second signal electrode (16).

    Abstract translation: 本发明涉及一种存储单元阵列，其能够降低信号电极的负载电容的寄生电容，并且具有构成铁电电容器并具有预定图案的铁电层; 一种制造存储单元阵列的方法和一种铁电存储器件。 在存储单元阵列中，由铁电电容器形成的存储单元以矩阵形式布置。 铁电电容器包括第一信号电极，沿与第一信号电极交叉的方向排列的第二信号电极，以及沿第一信号电极或第二信号电极线性设置的铁电层。 或者，铁电层可以仅设置在第一和第二信号电极的交叉区域中。

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