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    1.
    发明专利
    未知

    公开(公告)号：IT1228755B

    公开(公告)日：1991-07-03

    申请号：IT1991989

    申请日：1989-03-28

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： MENNITI PIETRO ,  BAIOCCHI ANTONELLA

    IPC: G05F1/10 ,  H02P7/00 ,  H02P8/12 ,  G01R

    Abstract: An electronic circuit (1) for measuring and controlling an electric current flowing through an inductive electric load (L), being of a type which comprises a first, field-effect power transistor (T2) connected to the load and a second, sensing transistor (Ts) having its source electrode (Ss) connected to the source electrode (S2) of the first transistor, further comprises a voltage comparator (3) having respective inputs connected to the corresponding drain electrodes (D2,Ds) of said transistors (T2,Ts), and an electronic switch (4) connected in ahead of the gate electrode (G2) of the power transistor (T2) and linked to the comparator (3) output.

    2.
    发明专利
    未知

    公开(公告)号：DE69125648D1

    公开(公告)日：1997-05-22

    申请号：DE69125648

    申请日：1991-05-27

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： BAIOCCHI ANTONELLA ,  ALZATI ANGELO ,  NOVELLI ALDO

    IPC: H03K5/1254 ,  H03K5/1252 ,  H03K5/01

    Abstract: A spike filtering circuit for a logic signal comprises a signal trasfer circuit formed by a first transfer (TG1) gate followed by a pair of inverters (INV1,INV2), functionally connected in series between the input terminal and the output terminal of the circuit and a second transfer gate (TG2) connected between the output terminal and the input node of the first of said two inverters (INV1). The two transfer gates (TG1,TG2) are driven in phase opposition to each other by means of a pair of control signals (CK,CK) in phase opposition to each other which are generated by a control circuit functioning in a feedback mode. Basically the control circuit is formed by an exclusive-OR gate (XOR) having two inputs connected to the output terminal of the circuit directly and through a delay network (d), respectively. Through an output node of the exlusive-OR gate (XOR) is produced a first control signal (2) from which the pair of control signals (CK,CK) in phase opposition to each other are derived by means of inverting stages. The delay network (d) introduces a delay after a transition of the signal on the output terminal of the circuit has occurred during which said first transfer gate (TG1) is momentarily disabled and said second transfer gate (TG2) is enabled in order to maintain on the output terminal the state reached with the first transition for a period of time sufficiently long to allow the decay of spikes which may have been generated by said transition of the logic signal. By employing a NAND gate (NAND) and an inverter (INV3) connected in cascade to the output of said exclusive-OR gate (XOR), the filtering circuit may be initialled by applying an enabling signal to a second input of said NAND gate.

    3.
    发明专利
    未知

    公开(公告)号：DE68922762D1

    公开(公告)日：1995-06-29

    申请号：DE68922762

    申请日：1989-01-20

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： BAIOCCHI ANTONELLA ,  ALZATI ANGELO

    IPC: H03K17/0412 ,  H03K17/687 ,  H03K17/695

    Abstract: A low-absorption circuit device (1) for controlling into the on state a power transistor (2), in particular a D MOS transistor having conventional gate (G), drain (D), and source (S) electrodes, and adapted to drive electrical loads (5) by changing over from an off state to an on state in which there appears on the gate electrode a predetermined voltage value Vcp), comprises a first turn-on circuit (6) connected to one pole of a voltage supply (Vcc), a second turn-on circuit (7) connected to another supply voltage pole (Vcp), and a comparator having respective inputs connected to the gate electrode (G) of the power transistor (2) and to a reference voltage pole (Vr) as well as respective outputs connected to each respective turn-on circuit (6,7) to activate said circuits alternately based on a comparison of the gate voltage of the power transistor with the predetermined reference voltage (Vr).

    4.
    发明专利
    未知

    公开(公告)号：IT8919919D0

    公开(公告)日：1989-03-28

    申请号：IT1991989

    申请日：1989-03-28

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： MENNITI PIETRO ,  BAIOCCHI ANTONELLA

    IPC: G05F1/10 ,  H02P7/00 ,  H02P8/12

    Abstract: An electronic circuit (1) for measuring and controlling an electric current flowing through an inductive electric load (L), being of a type which comprises a first, field-effect power transistor (T2) connected to the load and a second, sensing transistor (Ts) having its source electrode (Ss) connected to the source electrode (S2) of the first transistor, further comprises a voltage comparator (3) having respective inputs connected to the corresponding drain electrodes (D2,Ds) of said transistors (T2,Ts), and an electronic switch (4) connected in ahead of the gate electrode (G2) of the power transistor (T2) and linked to the comparator (3) output.

    6.
    发明专利
    未知

    公开(公告)号：IT1243301B

    公开(公告)日：1994-05-26

    申请号：IT8362290

    申请日：1990-05-25

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： BAIOCCHI ANTONELLA ,  ALZATI ANGELO ,  NOVELLI ALDO

    IPC: H03K5/1254 ,  H03K5/1252 ,  H03H

    Abstract: A spike filtering circuit for a logic signal comprises a signal trasfer circuit formed by a first transfer (TG1) gate followed by a pair of inverters (INV1,INV2), functionally connected in series between the input terminal and the output terminal of the circuit and a second transfer gate (TG2) connected between the output terminal and the input node of the first of said two inverters (INV1). The two transfer gates (TG1,TG2) are driven in phase opposition to each other by means of a pair of control signals (CK,CK) in phase opposition to each other which are generated by a control circuit functioning in a feedback mode. Basically the control circuit is formed by an exclusive-OR gate (XOR) having two inputs connected to the output terminal of the circuit directly and through a delay network (d), respectively. Through an output node of the exlusive-OR gate (XOR) is produced a first control signal (2) from which the pair of control signals (CK,CK) in phase opposition to each other are derived by means of inverting stages. The delay network (d) introduces a delay after a transition of the signal on the output terminal of the circuit has occurred during which said first transfer gate (TG1) is momentarily disabled and said second transfer gate (TG2) is enabled in order to maintain on the output terminal the state reached with the first transition for a period of time sufficiently long to allow the decay of spikes which may have been generated by said transition of the logic signal. By employing a NAND gate (NAND) and an inverter (INV3) connected in cascade to the output of said exclusive-OR gate (XOR), the filtering circuit may be initialled by applying an enabling signal to a second input of said NAND gate.

    10.
    发明专利
    未知

    公开(公告)号：DE68922762T2

    公开(公告)日：1995-10-12

    申请号：DE68922762

    申请日：1989-01-20

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： BAIOCCHI ANTONELLA ,  ALZATI ANGELO

    IPC: H03K17/0412 ,  H03K17/687 ,  H03K17/695

    Abstract: A low-absorption circuit device (1) for controlling into the on state a power transistor (2), in particular a D MOS transistor having conventional gate (G), drain (D), and source (S) electrodes, and adapted to drive electrical loads (5) by changing over from an off state to an on state in which there appears on the gate electrode a predetermined voltage value Vcp), comprises a first turn-on circuit (6) connected to one pole of a voltage supply (Vcc), a second turn-on circuit (7) connected to another supply voltage pole (Vcp), and a comparator having respective inputs connected to the gate electrode (G) of the power transistor (2) and to a reference voltage pole (Vr) as well as respective outputs connected to each respective turn-on circuit (6,7) to activate said circuits alternately based on a comparison of the gate voltage of the power transistor with the predetermined reference voltage (Vr).

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