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    4.
    发明专利
    未知

    公开(公告)号：IT8922819D0

    公开(公告)日：1989-12-22

    申请号：IT2281989

    申请日：1989-12-22

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： MURARI BRUNO ,  ROSSI DOMENICO ,  SAVINO PIERANTONIO

    IPC: G11B5/02 ,  G11B5/027 ,  H03F3/181 ,  H03F3/343 ,  H03F3/45 ,  H03F

    Abstract: A low-noise preamplifier stage, in particular for magnetic heads, which comprises a differential circuit (T5,T6) and a single-transistor output stage (T2). The differential stage has an intrinsic offset voltage, is ground-connectable and can be directly coupled to the magnetic head (L) , the two transistors forming the differential circuit (T5,T6) having different bias currents in order to reduce the input equivalent noise. The base terminal of the first transistor (T5) of the differential circuit defines an input (IN) of the stage which can be connected directly to a terminal of the magnetic head (L); the other terminal of the head can be connected directly to the ground. The base terminal of the other transistor (T6) of the differential circuit (T5,T6) is connected to the intermediate point of a pair of resistors (R1,R2) which are mutually connected in series between the single transistor of the output stage (T2) and a line at reference voltage. In this manner the differential stage (T5,T6) biases the output with its offset voltage without requiring additional components for this purpose.

    6.
    发明专利
    未知

    公开(公告)号：IT8822964D0

    公开(公告)日：1988-12-16

    申请号：IT2296488

    申请日：1988-12-16

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： ROSSI DOMENICO ,  VIANI ERMES ,  TORELLI GUIDO ,  MALOBERTI FRANCO

    IPC: G05F3/24 ,  G05F3/26

    Abstract: A current source circuit capable of generating two currents of opposite polarities. In order to generate the two currents, the circuit comprises a current source stage (M3-M5) including a current mirror and feeding a first output current (IOUT1) and an inverter stage (M6-M9) connected to the source stage and generating a second output current (IOUT2) with opposite polarity with respect to the first. The inverter stage comprises a current mirror (M6-M7) and a variable current source (M8-M9) defining a control electrode. In order to eliminate the differences in the amplitude of the output currents, the inverter stage comprises a memory element (C) connected to the control electrode so as to store an electrode controlling signal. Switch elements (SW1-SW4) are furthermore interposed between the first output and the second output so as to short-circuit them during the trimming step so that the two output currents are equal to one another while the memory element memorizes the control signal. This signal remains stored during the normal operation of the circuit.

    7.
    发明专利
    未知

    公开(公告)号：DE68925160D1

    公开(公告)日：1996-02-01

    申请号：DE68925160

    申请日：1989-06-08

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： ROSSI DOMENICO ,  DIAZZI CLAUDIO

    IPC: H02M3/07 ,  H02M3/155 ,  H02M3/156 ,  H02M7/538 ,  H03K17/06 ,  H03K17/082 ,  H03K17/60 ,  H03K17/08

    Abstract: The circuit comprises a tank capacitance (C) and a charge circuit supplied with the same voltage (Vs) as the bridge (M1, M2) and comprising an inductance (L) and a control transistor (T). There is also provided a control circuit (CC), which comprises an oscillator (OSC) controlling the periodic switching of control transistor (T) and a comparator (CP1) which controls the momentary clamping of control transistor (T) in the condition wherein the charge circuit is interrupted when the difference between the voltage across capacitance (C) and the power supply voltage exceeds a preset maximum value and the unclamping of the same transistor (T) when such difference falls below a preset minimum value. A further comparator (CP2) similarly clamps control transistor (T) if there is an excess current in the transistor itself. The generated voltage (Vp), which is higher than the supply voltage (Vs), controls, through a driver circuit (DS2), the gate of a power MOS transistor (M2).

    8.
    发明专利
    未知

    公开(公告)号：DE69101386T2

    公开(公告)日：1994-10-20

    申请号：DE69101386

    申请日：1991-01-07

    Applicant: SGS THOMSON MICROELECTRONICS ,  SIEMENS AUTOMOTIVE SA

    Inventor： CINI CARLO ,  ROSSI DOMENICO ,  SIMON MARC

    IPC: G01R19/00 ,  G01R31/26 ,  H03K17/08 ,  H03K17/12

    Abstract: The circuit for the measurement of the current in an MOS power transistor (M0) comprises second (M1) and third (M2) transistors connected in series. The latter two transistors are of the same type and are made using the same technology, but have a smaller surface area than the power transistor and they are connected in parallel with the latter. The two transistors connected in series have their gates connected to the gate of the power transistor. Means are provided for measuring the current in that one of the two transistors (M2) which is connected to the reference electrode of the power transistor. … …

    9.
    发明专利
    未知

    公开(公告)号：ES2051575T3

    公开(公告)日：1994-06-16

    申请号：ES91420005

    申请日：1991-01-07

    Applicant: SGS THOMSON MICROELECTRONICS ,  SIEMENS AUTOMOTIVE SA

    Inventor： CINI CARLO ,  ROSSI DOMENICO ,  SIMON MARC

    IPC: G01R19/00 ,  G01R31/26 ,  H03K17/08 ,  H03K17/12

    Abstract: The circuit for the measurement of the current in an MOS power transistor (M0) comprises second (M1) and third (M2) transistors connected in series. The latter two transistors are of the same type and are made using the same technology, but have a smaller surface area than the power transistor and they are connected in parallel with the latter. The two transistors connected in series have their gates connected to the gate of the power transistor. Means are provided for measuring the current in that one of the two transistors (M2) which is connected to the reference electrode of the power transistor. … …

    10.
    发明专利
    未知

    公开(公告)号：DE3884925T2

    公开(公告)日：1994-02-03

    申请号：DE3884925

    申请日：1988-11-18

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： ROSSI DOMENICO ,  PIETROBON GIOVANNI ,  STORTI SANDRO ,  CINI CARLO

    IPC: H02H7/08 ,  H03K17/00 ,  H03K17/06 ,  H03K17/24 ,  H03K17/695

    Abstract: A circuit (1) for holding a MOS power transistor (MP) in a conduction state on the occurrence of an outage in the voltage supply (VA), being of a type which comprises a first MOS transistor (M1) having its source (S1) connected to a line (2) of the voltage supply and its drain (D2) connected to the gate (GP) of the power transistor (MP), further comprises a diode (D) connected between the drain (D1) of the first transistor (M1) and the gate (GP) of the power transistor (MP), and a second transistor (M2) of the MOS type having its gate (G2) connected to the gate (G1) of the first transistor (M1) and its drain connected to the gate (GP) of the power transistor (MP). The circuit (1) prevents the gate capacitance (GP) of the power transistor from becoming discharged on a failure of the voltage supply (VA), thus holding that transistor in a conducting state.

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