公开(公告)号：EP0644544A1

公开(公告)日：1995-03-22

申请号：EP93830387.2

申请日：1993-09-21

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Moloney, David ,  Gadducci, Paolo ,  Betti, Giorgio ,  Alini, Roberto

IPC: G11B20/14 ,  H03M5/14

CPC classification number: H03M5/145 ,  G11B20/1426

Abstract: In a decoder for decoding a serial data stream, employing an extracted base clock signal, synchronous with an input, coded, serial data stream, a fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary clock signal for synthesizing a pre-decoded value produced by a first combinative logic network within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop, a pipelined operation is implemented by momentarily storing the bits that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock the processing by said first combinative network of the n-number of bits handled by the decoder. Each one of the two combinative logic networks is permitted to complete its decoding process within a full clock cycle in advance of the raising front of the outpunt sampling clock signal. With the same fabrication technology and therefore with the same propagation delay of the two combinative logic networks, the maximum operating spead may be doubled. A limited number of additional components are required to implement the pipelined operation of the invention.

Abstract translation: 在用于解码串行数据流的解码器中，采用提取的基本时钟信号，与输入，编码的串行数据流同步，用于对解码的输出数据流进行采样的一级频率时钟信号和用于合成预 由第二组合逻辑网络中的第一组合逻辑网络产生的解码值以产生被发送到输出采样触发器的解码值，流水线操作通过瞬时存储在第二组合逻辑中被处理的位来实现 并且通过预期同步基本时钟的两个完整周期，所述第一组合网络对由解码器处理的n个比特的比特进行处理。 允许两个组合逻辑网络中的每一个在提前采样时钟信号的前端之前在整个时钟周期内完成其解码过程。 使用相同的制造技术，因此具有相同的两个组合逻辑网络的传播延迟，最大操作频率可能增加一倍。 需要有限数量的附加部件来实现本发明的流水线操作。

公开(公告)号：EP0715239A1

公开(公告)日：1996-06-05

申请号：EP94830555.2

申请日：1994-11-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brianti, Francesco ,  Pisati, Valerio ,  Alini, Roberto ,  Moloney, David

IPC: G05F3/26

CPC classification number: G05F3/265 ,  G05F3/262

Abstract: A high-precision current generating circuit (1), particularly intended for a low-impedance circuit user, comprises a current mirror formed by a first (M1) and a second (M2) transistor of the MOS type, and a voltage regulator (4) having two terminals respectively connected to the drain terminals (D1,D2) of the two transistors (M1,M2) to maintain equal values of drain-source voltage (Vds1 and Vds2) on said transistors.

Abstract translation: 特别是用于低阻抗电路用户的高精度电流产生电路（1）包括由MOS型的第一（M1）和第二（M2）晶体管形成的电流镜和电压调节器（4） ）具有分别连接到两个晶体管（M1，M2）的漏极端子（D1，D2）的两个端子，以在所述晶体管上保持漏 - 源电压（Vds1和Vds2）的相等值。

公开(公告)号：EP0703663A1

公开(公告)日：1996-03-27

申请号：EP94830445.6

申请日：1994-09-21

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Moloney, David ,  Gadducci, Paolo

IPC: H03K5/13

CPC classification number: H03K5/131 ,  H03K5/133

Abstract: A programmable digital delay unit (20) presenting a number of cascade-connected delay blocks (22), and a number of controlled bypass elements (23, 24), one for each delay block (22). Each bypass element presents a bypass line (23) and a multiplexer (24) for selectively connecting the input or output of the respective delay block to the input of the next delay block (22). The delay blocks (22) are formed by the cascade connection of flip-flops (28), and the number of flip-flops (28) in each successive delay block (22), from the input of the delay unit (20), decreases in an arithmetic progression to the power of two, so that the selection signals (S₀-S₃) for the respective multiplexers (24) represent the bits of a digital word (M) specifying the required delay.

Abstract translation: 一个可编程数字延迟单元（20），其呈现多个级联连接的延迟块（22），以及多个受控旁路元件（23,24），每个延迟块（22）一个。 每个旁路元件呈现旁路管线（23）和多路复用器（24），用于选择性地将相应延迟块的输入或输出连接到下一个延迟块（22）的输入端。 延迟块（22）由触发器（28）的级联连接和每个连续延迟块（22）中的触发器（28）的数量从延迟单元（20）的输入端形成， 算术进展减少到2的幂，使得用于各个多路复用器（24）的选择信号（S0-S3）表示指定所需延迟的数字字（M）的位。

公开(公告)号：EP0684608A1

公开(公告)日：1995-11-29

申请号：EP94830235.1

申请日：1994-05-23

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Zuffada, Maurizio ,  Gadducci, Paolo ,  Moloney, David ,  Pisati, Valerio

IPC: G11B21/10 ,  G11B5/596 ,  G11B20/10

CPC classification number: G11B20/10009 ,  G11B21/106

Abstract: The device is to be used with a parallel architecture PRML reading apparatus comprising a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel processing channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two processing channels (24, 34) comprise respective analog-digital converters (26, 36) and respective Viterbi detectors (27, 37) and operate according to sampling sequences that alternate with one another. The device (30) for processing the servo signals comprises a rectifier (31) connected to the outputs of said analog-digital converters (26, 36) and an integrator (32).

Abstract translation: 该装置是用一个并行架构PRML读取装置，包括一个可变增益输入放大器（21），一个低通模拟滤波器（22），横向模拟滤波器（23）和两个不同的和并行处理通道（24中使用 ，34）横向模拟滤波器（23）和解码器，以RLL NRZ（25之间）。 所述两个处理通道（24，34）包括respectivement模拟 - 数字转换器（26，36）和相应的Viterbi检测（27，37）和操作根据采样序列并彼此交替。 用于处理所述伺服信号的装置（30）包括连接到所述模拟 - 数字转换器的输出（26,36），并在积分器（32）的整流器（31）。

公开(公告)号：EP0613147A1

公开(公告)日：1994-08-31

申请号：EP93830080.3

申请日：1993-02-26

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Alini, Roberto ,  Moloney, David ,  Gornati, Silvano ,  Portaluri, Salvatore

IPC: G11C5/00

CPC classification number: G06F13/4221

Abstract: A shared register circuit structure coupled to data transmission lines through interfacing circuit means of the serial type which are connected to said registers by an address and data transmission bus. The structure includes at least one transmission line for select signals to alternatively use address information or data information.

Abstract translation: 通过接口被连接到所述串行类型的电路装置，耦合到数据传输线共享寄存器电路结构，在地址和数据传输总线寄存器通过。 该结构包括至少一个传输线选择信号以交替地使用地址信息或数据信息。

公开(公告)号：EP0482495B1

公开(公告)日：1998-07-08

申请号：EP91117649.3

申请日：1991-10-16

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Moloney, David ,  Zuffada, Maurizio ,  Vai, Gianfranco ,  Sacchi, Fabrizio

IPC: G06F7/00 ,  G06F11/08

CPC classification number: G06F11/0763 ,  G06F7/00 ,  G06F11/085 ,  G06F11/28

公开(公告)号：EP0684605A1

公开(公告)日：1995-11-29

申请号：EP94830236.9

申请日：1994-05-23

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Zuffada, Maurizio ,  Gadducci, Paolo ,  Moloney, David ,  Alini, Roberto

IPC: G11B20/10 ,  G11B5/09

CPC classification number: G11B5/09 ,  G11B20/10009

Abstract: The device comprises a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel sampling channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two sampling channels (24, 34) comprise, each of them, an analog-digital converter (26, 36) and a Viterbi detector (27, 37) arranged in succession one after the other and operating according to sampling sequences that alternate with one another.

Abstract translation: 该装置包括一个可变增益输入放大器（21），一个低通模拟滤波器（22），横向模拟滤波器（23）和横向模拟滤波器之间插入两个不同且平行的采样信道（24，34）（23 解码器）中，在RLL NRZ（25）。 两个采样信道（24，34）包括，他们每个人的，安装在模拟 - 数字转换器（26，36）和一个维特比检测器（27，37）相继一前一后并雅丁到采样序列操作做交替 彼此。

公开(公告)号：EP0492338A3

公开(公告)日：1993-10-27

申请号：EP91121516.8

申请日：1991-12-16

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Vai, Gianfranco ,  Zuffada, Maurizio ,  Sacchi, Fabrizio ,  Moloney, David ,  Betti, Giorgio

IPC: H03K3/282

CPC classification number: H03K3/2821

Abstract: A circuit device (1) for phasing an oscillator (2), which comprises a multivibrator (3) having a transistor pair (Q1,Q2) with the emitters (E1,E2) coupled through a capacitor (C), comprises a normally open electronic switch (SW) controlled by a drive signal (IN) to close and inhibit the oscillator (2). This switch connects a voltage divider to the base of a transistor (Q7) connected to one (E2) of the emitters to interrupt the loop positive feedback of the oscillator (2) upon the voltage across the capacitor reaching a predetermined value.

公开(公告)号：EP0490016A1

公开(公告)日：1992-06-17

申请号：EP90830579.0

申请日：1990-12-12

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Sacchi, Fabrizio ,  Zuffada, Maurizio ,  Vai, Gianfranco ,  Moloney, David

IPC: H03G1/00 ,  H03G1/04 ,  G05F3/22

CPC classification number: H03G1/04 ,  G05F3/225 ,  H03G1/0023

Abstract: A circuit particularly useful in AGC systems, produces an output current (I OUT ) which is proportional to the difference between a signal voltage (V AGC ) and a reference voltage (V R ) which is practically independent of temperature, by being a function of a ratio among actual values of integrated resistances and of a ratio among substantially temperature-stable voltages. The effects of temperature dependent value of integrated resistances and of temperature-dependent electrical characteristics of integrated semiconductor devices are compensated in order to produce the desired temperature-independent output current which may usefully be utilized for implementing an automatic gain control.

Abstract translation: 所有这实际上与温度无关，通过作为比之间的函数的输出电流（I OUT）的所有成比例的信号电压（V AGC）和参考电压（VR）之间的差的电路中的AGC系统是特别有用的，可生产 的集成termoresistencias和基本上温度稳定的电压之间的比率的实际值。 的集成termoresistencias和的集成半导体器件的依赖于温度的电特性的温度依赖值的影响，以便产生所需的温度无关的输出电流可以有用地用于实施的自动增益控制进行补偿。

公开(公告)号：EP0751457A1

公开(公告)日：1997-01-02

申请号：EP95830278.8

申请日：1995-06-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Gadducci, Paolo ,  Moloney, David ,  Brianti, Francesco ,  Pisati, Valerio

IPC: G06F7/02

CPC classification number: G06F7/026

Abstract: The invention relates to a basic cell (11) for comparing a first and a second digital signal (A, B), of the type having at least a first and a second input (I1, I2) and a first and a second output (O3, O4) and comprising at least one logic gate (14) receiving digital signals (A, B) at a first and a second signal input (IS1, IS2), and which comprises at least a first and a second controlled switch (P1, P2) inserted in parallel with each other between the output terminal of the logic gate (14) and the second output (O4) from the cell (11), the first switch (P1) being also connected between the first input (I1) and the first output (O3) of the cell (11) and the second switch (P2) being also connected between the second input (I2) and the second output (O4) of the cell (11).
The invention also relates to a digital comparator (9) comprising a plurality of basic cells according to the invention.

Abstract translation: 本发明涉及的基本单元（11），用于比较第一和第二数字信号（A，B），其具有至少一个第一和一个第二输入（I1，I2）和第一和第二输出的类型的（ O3，O4）和包括至少一个逻辑门（14）在接收到数字信号（A，B）在第一和第二信号输入端（IS1，IS2），并且其包括至少一个第一和一个第二可控开关（P1 ，P2）插入到彼此平行的逻辑门（14）和从所述小区（11），第一开关（P1的第二输出端（O4）的输出端子之间），以便被连接在第一输入（I1之间） 并由此被连接在第二输入（I 2）和电池（11）的第二输出（O4）之间的单元（11）和所述第二开关（P2）的第一输出（O3）。 因此本发明涉及到一个数字比较器（9）包括gemäß发明基本单元的复数。