公开(公告)号：EP0766255A1

公开(公告)日：1997-04-02

申请号：EP95830406.5

申请日：1995-09-29

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Sali, Mauro ,  Tassan Caser, Fabio ,  Schippers, Stefan

IPC: G11C16/06 ,  G11C29/00

CPC classification number: G11C16/24 ,  G11C16/10 ,  G11C29/34

Abstract: A method for the parallel programming of memory words in electrically programmable non-volatile semiconductor memory devices comprising at least one matrix of floating gate memory cells with corresponding drain terminals heading columns or bit lines of the matrix which are supplied during the single word programming stage with a drain voltage which is boosted with respect to a supply voltage (Vcc). During the parallel programming stage the supply voltage is used as a drain voltage.
Switching is provided between the drain supply using the boosted drain voltage and the supply voltage (Vcc) during the transient between single word programming and parallel programming.

Abstract translation: 一种用于在电可编程非易失性半导体存储器件中对存储器字进行并行编程的方法，包括至少一个浮动栅极存储器单元的矩阵，其具有在单个字编程阶段期间提供的矩阵的相应漏极端子标题列或位线， 相对于电源电压（Vcc）升高的漏极电压。 在并行编程阶段，电源电压用作漏极电压。 在单字编程和并行编程之间的瞬态期间，在使用升压漏极电压的漏极电源和电源电压（Vcc）之间提供开关。

公开(公告)号：EP0753859A1

公开(公告)日：1997-01-15

申请号：EP95830302.6

申请日：1995-07-14

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Sali, Mauro ,  Dallabora, Marco ,  Carrera, Marcello

IPC: G11C16/06 ,  G11C29/00

CPC classification number: G11C16/3459 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/3454 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5006

Abstract: A method for setting the threshold voltage of a reference memory cell (RMC) of a memory device is described, the reference memory cell (RMC) being used as a reference current generator for generating a reference current which is compared by a sensing circuit (1,2,3) of the memory device with currents sunk by memory cells to be sensed, belonging to a memory matrix (MM) of the memory device. The method comprises a first step in which the reference memory cell (RMC) is submitted to a change in its threshold voltage, and a second step in which the threshold voltage of the reference memory cell (RMC) is verified. The second step provides for performing a sensing of the reference memory cell (RMC) using a memory cell (MC) with known threshold voltage (V TUV ) belonging to the memory matrix (MM) as a reference current generator for generating a current (IC) which is compared by the sensing circuit (1,2,3) with the current (IR) sunk by the reference memory cell (RMC).

Abstract translation: 描述了用于设置存储器件的参考存储单元（RMC）的阈值电压的方法，参考存储单元（RMC）用作参考电流发生器，用于产生参考电流，该参考电流由感测电路（1 ，2,3）的存储器件，存储器件的存储器矩阵（MM）属于存储器器件的存储器矩阵（MM）。 该方法包括第一步骤，其中参考存储器单元（RMC）被提交到其阈值电压的改变，以及第二步骤，其中验证参考存储单元（RMC）的阈值电压。 第二步提供使用具有属于存储矩阵（MM）的已知阈值电压（VTUV）的存储单元（MC）作为参考电流发生器来执行对参考存储单元（RMC）的感测作为参考电流发生器，用于产生电流（IC） 其通过感测电路（1,2,3）与由参考存储器单元（RMC）沉没的当前（IR）进行比较。

公开(公告)号：EP0564751A1

公开(公告)日：1993-10-13

申请号：EP92830177.9

申请日：1992-04-10

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Golla, Carla ,  Sali, Mauro

IPC: H03H17/06 ,  H03H17/02

CPC classification number: H03H17/0607

Abstract: A high-resolution digital filter of a type which comprises a memory structure receiving as input a sampled digital signal, and an adder chain with delay blocks therebetween, the adders being connected to memory outputs to convert the input signal into an output signal having predetermined frequency response characteristics, has the memory structure made up of at least one pair of non-volatile memories (3,4) being input each one portion (x(n)₁,x(n)₂) only of the sampled signal.

Abstract translation: 一种高分辨率数字滤波器，它包括一个接收采样数字信号作为输入的存储器结构，以及一个在其之间具有延迟块的加法器链，加法器连接到存储器输出，以将输入信号转换为具有预定频率的输出信号 响应特性具有仅由采样信号每一部分（x（n）1，x（n）2）输入的至少一对非易失性存储器（3,4）构成的存储器结构。

公开(公告)号：EP0564751B1

公开(公告)日：1997-10-08

申请号：EP92830177.9

申请日：1992-04-10

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Golla, Carla ,  Sali, Mauro

IPC: H03H17/06 ,  H03H17/02

CPC classification number: H03H17/0607

公开(公告)号：EP0782147A1

公开(公告)日：1997-07-02

申请号：EP95830555.9

申请日：1995-12-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Sali, Mauro ,  Cane, Marcello ,  Villa, Corrado

IPC: G11C16/06

CPC classification number: G11C16/3495 ,  G11C16/349 ,  G11C29/88

Abstract: The invention relates to a programming method and device for detecting an error and inhibiting writing into a memory. The invention provides for the inclusion, in the standard programming method, of a checking step for interrupting the programming procedure and generating an error signal detecting the attempted overwriting of a "0" with a "1".
The checking step of the inventive programming method provides for an initial comparison between the contents of a plurality of bits being programmed and a corresponding plurality of bits to be written in, the generation of an error signal upon detection of homolog pairs with a value of "one", and the interruption of the byte programming procedure to prevent a "1" from being written over a "0".

Abstract translation: 本发明涉及一种用于检测错误并禁止写入存储器的编程方法和装置。 本发明提供了在标准编程方法中包括用于中断编程过程的检查步骤，并且生成检测到用“1”尝试重写“0”的错误信号。 本发明的编程方法的检查步骤提供了正被编程的多个比特的内容和要写入的对应的多个比特之间的初始比较，在检测到同位素对时产生错误信号，其值为“ 一个“以及字节编程过程的中断，以防止在”0“上写入”1“。

公开(公告)号：EP0571693B1

公开(公告)日：1996-04-10

申请号：EP92830267.8

申请日：1992-05-27

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Golla, Carla ,  Sali, Mauro

IPC: G06F7/50

CPC classification number: G06F7/509

公开(公告)号：EP0798735A1

公开(公告)日：1997-10-01

申请号：EP96830174.7

申请日：1996-03-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Tassan Caser, Fabio ,  Sali, Mauro ,  Cane, Marcello

IPC: G11C11/00 ,  G11C16/06 ,  G11C8/00

CPC classification number: G11C8/10 ,  G11C16/08

Abstract: The invention relates to a row decoding circuit (1) for an electrically programmable and erasable semiconductor non-volatile storage device of the type which comprises a matrix (2) of memory cells laid out as cell rows (WL) and columns and is divided into sectors, said circuit being input row decode signals (p,ly,lx,ls) and supply voltages (Vpcxs, pgate) in order to drive an output stage (8) incorporating a complementary pair of high-voltage MOS transistors (M15,M13) of the pull-up and pull-down type, respectively, which are connected to form an output terminal (U) connected to the rows (WL) of one sector of the matrix (2), characterized in that a MOS transistor (M9) of the P-channel depletion type with enhanced gate oxide is provided between the output terminal (U) and the pull-down transistor (M13). The control terminal of the depletion transistor (M9) forms a further input (H) of the circuit (1).

Abstract translation: 本发明涉及到一个行解码电路（1），用于其包括布置为单元行（WL）和列的存储单元（2）的矩阵和被分成类型中的电可编程和可擦除的半导体非易失性存储装置 扇区，所述电路被输入行译码信号（p，LY，LX，LS），以便和电源电压（Vpcxs，PGATE）以驱动输出级（8）包含一对互补的高电压MOS晶体管的（M15，M13 ）上拉的和下拉的类型，分别被连接到形成在输出端（U）连接到矩阵（2），其特征做了MOS晶体管的一个扇区中的行（WL）（M9 ）P沟道耗尽型具有增强栅氧化层的被输出端（U）和所述下拉晶体管（M13）之间。 所述耗尽型晶体管（M9）的控制端子构成电路（1）的另一个输入端（H）。

公开(公告)号：EP0564752B1

公开(公告)日：1996-07-24

申请号：EP92830178.7

申请日：1992-04-10

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Golla, Carla ,  Sali, Mauro

IPC: G06F7/52

CPC classification number: G06F7/5312

公开(公告)号：EP0571694B1

公开(公告)日：1995-12-06

申请号：EP92830268.6

申请日：1992-05-27

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Golla, Carla ,  Sali, Mauro

IPC: G06F7/50

CPC classification number: G06F7/509 ,  G06F7/506

公开(公告)号：EP0571693A1

公开(公告)日：1993-12-01

申请号：EP92830267.8

申请日：1992-05-27

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Golla, Carla ,  Sali, Mauro

IPC: G06F7/50

CPC classification number: G06F7/509

Abstract: A fast adder chain, of a type intended for adding together at least one pair of digital words (X,Y) and comprising a plurality of cascaded adder blocks, has in each block (2) computation means (HA,FA) for obtaining the pseudosum of said pair of digital words (X,Y) and means (10,11) for storing and transmitting the pseudosum (SOMi) to the next block and the pseudocarry (Ci) from the computation to the chain end.

Abstract translation: 用于将至少一对数字字（X，Y）加在一起并包括多个级联加法器块的类型的快速加法器链在每个块（2）中具有计算装置（HA，FA），用于获得 所述一对数字字（X，Y）的假拟数和用于存储和传送假（SOMi）到下一个块和假计算（Ci）从计算到链端的装置（10,11）。