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    Supply voltages switch circuit
    2.
    发明公开
    Supply voltages switch circuit 失效
    SchaltkreisfürBetriebsspannungen

    公开(公告)号：EP0782268A2

    公开(公告)日：1997-07-02

    申请号：EP96830353.7

    申请日：1996-06-20

    Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

    Inventor： Villa, Corrado ,  Bettini, Luigi ,  Bartoli, Simone

    IPC: H03K17/693

    CPC classification number: G11C5/143 ,  G11C16/12 ,  H03K17/6871 ,  H03K17/693

    Abstract: A circuit for switching between supply voltages and in particular for non-volatile flash memory devices and of the type comprising a first and a second circuit branch each incorporating a pair of transistors (MA,MB;Mc,MD) connected in series provides that at least one branch (2) of the circuit be structured with a bridge circuit made up of P-channel MOS transistors. The bridge is made of a first (5) and a second (4) pairs of transistors (M1,M2,M3,M4) connected between a first supply voltage reference (SUPPLY1) and a common node (D). The first pair (5) comprises transistors (M1,M2) bigger than the transistors (M3,M4) of the second pair (4) while between the transistors (M3,M4) making up the second pair (4) is inserted a pair of resistors (R1,R2). Between the pair of resistors (R1,R2) there is an interconnection node (F) connected to a corresponding interconnection node (E) between the transistors (M1,M2) of the first pair (5).

    Abstract translation: 用于在电源电压之间切换的电路，特别是用于非易失性闪速存储器件的电路，以及包括连接在一起的一对晶体管（MA，MB，Mc，MD）的第一和第二电路支路的类型的电路， 电路的至少一个分支（2）由具有P沟道MOS晶体管的桥接电路构成。 该桥由连接在第一电源电压基准（SUPPLY1）和公共节点（D）之间的第一（5）和第二（4）对晶体管（M1，M2，M3，M4）组成。 第一对（5）包括大于第二对（4）的晶体管（M3，M4）的晶体管（M1，M2），而构成第二对（4）的晶体管（M3，M4）之间插入一对 的电阻（R1，R2）。 在一对电阻器（R1，R2）之间存在连接到第一对（5）的晶体管（M1，M2）之间的对应互连节点（E）的互连节点（F）。

    Flash EEPROM with controlled discharge time of the word lines and source potentials after erase
    3.
    发明公开
    Flash EEPROM with controlled discharge time of the word lines and source potentials after erase 失效
    快闪EEPROM与字线的控制的放电时间和源删除后电压

    公开(公告)号：EP0757356A1

    公开(公告)日：1997-02-05

    申请号：EP95830348.9

    申请日：1995-07-31

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Sali, Mauro ,  Villa, Corrado ,  Carrera, Marcello

    IPC: G11C16/06

    CPC classification number: G11C16/08

    Abstract: A Flash EEPROM comprises: at least one memory sector (S1-S8) comprising a plurality of rows (WL0-WL255) and columns (BL0-BL1024) of memory cells (MC); at least one negative voltage generator means (NP1-NP8) for generating a negative voltage (VP1-VP8) commonly charging said plurality of rows (WL0-WL255) to a negative potential during an erase pulse for erasing the memory cells (MC) of said at least one memory sector (S1-S8); control logic means (COM,SEQ) activating said negative voltage generator means (NP1-NP8) at the beginning of said erase pulse and deactivating said negative voltage generator means (NP1-NP8) at the end of the erase pulse. The Flash EEPROM comprises means (CC,CHC,DCHC) for controlling a discharge time of the rows (WL0-WL255) of said at least one memory sector (S1-S8) at the end of said erase pulse.

    Abstract translation: 快速EEPROM包括：至少一个存储器扇区（S1-S8），包括存储单元的行（WL0-WL255）和列（BL0-BL1024）的多个（MC）; 至少一个负电压发生器装置（NP1-NP8），用于在擦除脉冲期间产生负电压（VP1-VP8）通常充电行（WL0-WL255）到一个负电位的所述多个用于擦除的存储器单元（MC） 所述至少一个存储器扇区（S1-S8）; 控制逻辑装置（COM，SEQ）活化，在所述的开始所述负电压发生器装置（NP1-NP8）擦除脉冲和去激活所述在所述擦除脉冲结束负电压生成手段（NP1-NP8）。 快速EEPROM包括装置（CC，CHC，DCHC），用于在所述的端部控制的行。所述的（WL0-WL255）至少一个存储器扇区（S1-S8）的放电时间擦除脉冲。

    Negative word line voltage regulation circuit for electrically erasable semiconductor memory devices
    4.
    发明公开
    Negative word line voltage regulation circuit for electrically erasable semiconductor memory devices 失效
    负面的Wortleitung-SpannungsregelungschaltungfürelektrischlöschbareHalbleiterspeicheranordnungen

    公开(公告)号：EP0750314A1

    公开(公告)日：1996-12-27

    申请号：EP95830253.1

    申请日：1995-06-19

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Sali, Mauro ,  Villa, Corrado ,  Carrera, Marcello

    IPC: G11C16/06

    CPC classification number: G11C16/30

    Abstract: A negative word line voltage regulation circuit, integratable in an electrically erasable semiconductor memory device for regulating a negative word line voltage (01-08) to be supplied to word lines (WL) of the memory device during an electrical erasure of the memory device, comprises an operational amplifier (2) with a first input (3) coupled to a reference voltage (GND), a second input (4) coupled to the negative word line voltage (01-08) and an output (6) controlling a voltage regulation branch (8,13,14,151-158), connected between an external power supply (VCC) and the negative word line voltage (01-08), to provide a regulation current (IR) for regulating the negative word line voltage (01-08). The output (6) of the operational amplifier (2) also controls a voltage sensing branch (7,9,10,121-128), connected between the external power supply (VCC) and the negative word line voltage (01-08), to provide a sensing signal (11) coupled to the second input (4) of the operational amplifier (2).

    Abstract translation: 一种负字形电压调节电路，可整合在电可擦除半导体存储器件中，用于在存储器件的电擦除期间调节要提供给存储器件的字线（WL）的负字线电压（01-08） 包括具有耦合到参考电压（GND）的第一输入（3）的运算放大器（2），耦合到所述负字线电压（01-08）的第二输入（4）和控制电压 连接在外部电源（VCC）和负字线电压（01-08）之间的调节分支（8,13,14,151-158），以提供用于调节负字线电压（01）的调节电流（IR） -08）。 运算放大器（2）的输出（6）还控制连接在外部电源（VCC）和负字线电压（01-08）之间的电压感测支路（7,9,10,121-128）， 提供耦合到运算放大器（2）的第二输入（4）的感测信号（11）。

    Regulation of the output voltage of a voltage multiplier
    5.
    发明公开
    Regulation of the output voltage of a voltage multiplier 失效
    Ausgangsspannungs-Regulierung eines Spannungsvervielfachers。

    公开(公告)号：EP0350462A2

    公开(公告)日：1990-01-10

    申请号：EP89830291.4

    申请日：1989-06-23

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Olivo, Marco ,  Pascucci, Luigi ,  Villa, Corrado

    IPC: H02M3/07 ,  G11C5/00

    CPC classification number: G11C5/145 ,  G11C16/30 ,  H02M3/073

    Abstract: The regulation of the output voltage of a voltage multi­plier driven by a ring oscillator, an inverter of which is substituted by a NOR gate for providing a terminal through which stopping the oscillation, is effected by controlling the oscillation frequency in function of the current delivered by the voltage multiplier by means of a transistor T1 working as a current generator connected in series with a regulating chain of series-connected diodes by biasing the gate of the transistor with a constant voltage Vref, thus imposing a reference current Iref through the transistor. The voltage signal across the transistor is fed to the in­put of a first inverter with a preset triggering threshold and the output signal of the inverter is fed through an am­plifying and phase-regenerating stage to said terminal for stopping the oscillation of said NOR gate of the ring oscil­lator. When the discharge current through the regulating chain becomes greater than the imposed current Iref, across the transistor T1 a voltage signal develops which, beyond a certain threshold, determines the switching of the inverter and, through the amplifying and phase-regenerating stage, causes a stop of the oscillation which resumes only when conduction through the regulating chain stops. At steady state the oscillation frequency will result controlled so as to maintain constant the output voltage of the voltage multiplier and to limit the discharge current through the regulating chain thus limiting power consumption.

    Abstract translation: 由环形振荡器驱动的电压倍增器的输出电压的调节是通过控制振荡频率来实现的，该环形振荡器的逆变器由NOR门用于提供停止振荡的端子， 电压倍增器借助于作为电流发生器的晶体管T1，其通过以恒定电压Vref偏置晶体管的栅极而与串联二极管的调节链串联连接，从而通过晶体管施加参考电流Iref。 晶体管两端的电压信号以预置的触发阈值馈送到第一反相器的输入，反相器的输出信号通过放大和相位再生级馈送到所述端子，以停止所述NOR门的振荡 环形振荡器。 当通过调节链的放电电流变得大于施加的电流Iref时，跨越晶体管T1产生电压信号，超过一定阈值，确定逆变器的开关，通过放大和相位再生阶段， 仅当通过调节链的导通停止时才恢复振荡的停止。 在稳态下，振荡频率将受到控制，以保持电压倍增器的输出电压不变，并限制放电电流通过调节链，从而限制功耗。

    Flash EEPROM with on-chip erase source voltage generator
    7.
    发明公开
    Flash EEPROM with on-chip erase source voltage generator 失效
    闪存EEPROM芯片-Löschung-Source-Spannungs发电机

    公开(公告)号：EP0756286A1

    公开(公告)日：1997-01-29

    申请号：EP95830317.4

    申请日：1995-07-24

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Dallabora, Marco ,  Villa, Corrado ,  Bettini, Luigi

    IPC: G11C16/06 ,  G11C5/14

    CPC classification number: G11C16/16 ,  G11C5/147

    Abstract: A Flash EEPROM comprises negative voltage generator means (8) for generating a negative voltage to be supplied to control gate electrodes (CG) of memory cells (2) for erasing the memory cells (2). The Flash EEPROM comprises first positive voltage generator means (10) for generating a first positive voltage (VO), independent from an external power supply (VCC) of the Flash EEPROM, to be supplied to source regions (S) of the memory cells (2) during erasing.

    Abstract translation: 闪存EEPROM包括负电压发生器装置（8），用于产生用于擦除存储单元（2）的存储单元（2）的控制栅电极（CG）的负电压。 闪存EEPROM包括用于产生独立于闪存EEPROM的外部电源（VCC）的第一正电压（VO）的第一正电压发生器装置（10），以提供给存储器单元的源极区域（S） 2）擦除期间。

    CMOS voltage multiplier
    10.
    发明公开
    CMOS voltage multiplier 失效
    CMOS电压乘法器

    公开(公告)号：EP0349495A3

    公开(公告)日：1992-03-25

    申请号：EP89830269.0

    申请日：1989-06-16

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Olivo, Marco ,  Pascucci, Luigi ,  Villa, Corrado

    IPC: G11C5/00 ,  G11C17/00 ,  G11C16/06 ,  G11C5/14 ,  H02M3/07

    CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/073

    Abstract: A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.

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