公开(公告)号：EP0797209A1

公开(公告)日：1997-09-24

申请号：EP96830129.1

申请日：1996-03-20

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Fontana, Marco ,  Barcella, Antonio

IPC: G11C7/00

CPC classification number: G11C7/1006

Abstract: A non-volatile memory device, having the particularity that it comprises an internal bus (3) for the transmission of data and other information of the memory to output pads (4); timer means (8); and means (5, 5') for enabling/disabling access to the internal bus; the timer means (8) time the internal bus to transmit information signals of the memory device that originate from local auxiliary lines (7) over the internal bus (3) when the bus is in an inactive period during a normal memory data reading cycle; the timer means (8) drive the enabling/disabling means (5, 5') to allow/deny access to the internal bus (3) on the part of the information signals or of the data from or to the memory.

Abstract translation: 一种非易失性存储器件，其特征在于它包括用于将数据和存储器的其它信息传送到输出焊盘（4）的内部总线（3）。 定时器装置（8）; 以及用于启用/禁用访问所述内部总线的装置（5,5'）; 当总线在正常存储器数据读取周期期间处于非活动期间时，定时器装置（8）使内部总线在内部总线（3）上传送来自本地辅助线（7）的存储器件的信息信号; 定时器装置（8）驱动启用/禁用装置（5,5'）以允许/拒绝部分信息信号或来自或向存储器的数据的内部总线（3）的访问。

公开(公告)号：EP0768672A1

公开(公告)日：1997-04-16

申请号：EP95830405.7

申请日：1995-09-29

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Fontana, Marco ,  Barcella, Antonio

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C8/14

Abstract: The memory device in accordance with the present invention has hierarchical row decoding architecture and comprises at least one main decoder MD and a plurality of secondary decoders SD. The decoders SD have outputs coupled to a plurality of word lines WL respectively through a plurality of auxiliary lines AL having first ends T1 respectively connected to said outputs and second ends T2 respectively connected to intermediate points IT of the word lines WL.

Abstract translation: 根据本发明的存储器件具有分级行解码架构，并且包括至少一个主解码器MD和多个辅助解码器SD。 解码器SD具有通过分别连接到所述输出的第一端T1和分别连接到字线WL的中间点IT的第二端T2的多条辅助线AL分别耦合到多条字线WL的输出。

公开(公告)号：EP0798729A1

公开(公告)日：1997-10-01

申请号：EP96830160.6

申请日：1996-03-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Fontana, Marco ,  Barcella, Antonio

IPC: G11C7/00 ,  G11C16/06

CPC classification number: G11C7/14 ,  G11C16/28

Abstract: A reference word line and data propagation reproduction circuit, particularly for non-volatile memories provided with hierarchical decoders, characterized in that the memory is divided into at least two memory half-matrices that are arranged on different half-planes, and in that the circuit comprises, for each one of the at least two memory half-matrices, a reference unit (3 i ) for each one of the at least two memory half-matrices and an associated unit (4) for reproducing the propagation of the signals along the reference unit, the reference unit (3 i ) and the associated propagation reproduction unit (4) having a structure that is identical to each generic word line of the memory device, the reference and propagation reproduction units of one of the at least two memory half-matrices being activatable upon selection of a memory cell in the other one of the at least two memory half-matrices, in order to provide a reference that is synchronous and symmetrical with respect to the selection of the memory cell for reading it and so as to preset, according to the propagation reproduction unit (4), the conditions for starting correct and certain reading of the selected memory cell.

Abstract translation: 参考字线和数据传播再生电路，尤其是用于设置有分层解码器，在DASS特点非易失性存储器管芯存储器被划分成至少两个存储器的半矩阵也被布置在不同的半平面，并且在DASS模具电路 包括，对于所述至少两个存储器的半矩阵中的每一个，对于所述至少两个存储器中的每一个半矩阵和相关联的单元（4），用于沿着所述参考再现的信号的传播的参考单元的（3R） 单元，参考单元（3I）和相关的传播再现单元（4）具有这样的结构确实是相同的存储装置中，至少两个存储器中的一个半矩阵的参考和传播再现单元中的每个通用字线 是在一个存储器单元的选择激活的至少两个存储器的半矩阵中的另一个，以提供一个参考并是同步和对称相对于所述选择 用于读取它和所述存储器单元的，以预先设定，gemäß到传播再现单元（4），用于启动和所选择的存储单元的正确阅读某些条件。

公开(公告)号：EP0756379A1

公开(公告)日：1997-01-29

申请号：EP95830337.2

申请日：1995-07-28

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Barcella, Antonio ,  Fontana, Marco

IPC: H03K3/356 ,  G11C16/06

CPC classification number: G11C7/20 ,  H03K3/356008 ,  H03K3/356104

Abstract: A latch circuit (1) that is intentionally imbalanced, so that a first output (6) reaches ground voltage and a second output (7) reaches a supply voltage; and a fully static low-consumption fuse circuit the particularity whereof resides in that it comprises the intentionally unbalanced latch circuit (1) and a reversing branch that comprises the fuse to be programmed (6) and is adapted to reverse the operation of the latch circuit, so that in the virgin state the fuse (9) connects the second output (7) of the latch circuit (1) to the ground voltage and connects the first output (6) to the supply voltage.

Abstract translation: 一种有意不平衡的锁存电路（1），使得第一输出端（6）达到接地电压，第二输出端（7）达到电源电压; 以及一种完全静态的低功耗熔断器电路，其特征在于它包括有意不平衡的锁存电路（1）和一个包括要被编程的熔丝（6）的反向分支，并且适于反转锁存电路的操作 ，使得在原始状态下，熔丝（9）将锁存电路（1）的第二输出（7）连接到接地电压，并将第一输出（6）连接到电源电压。

公开(公告)号：EP0681293A1

公开(公告)日：1995-11-08

申请号：EP94830209.6

申请日：1994-05-03

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Barcella, Antonio

IPC: G11C7/00 ,  G11C7/06

CPC classification number: G11C7/062

Abstract: The differential input stage of a sense amplifier is provided with a positive feedback for introducing a predefinable hysteresis that will prevent spurious switchings of the output of the sense amplifier, enhancing noise immunity. The positive feedback is realized by employing an inverting amplifying stage, which will introduce an hysteresis on one of the two switching phases. The thresholds of the sense amplifier may be made symmetric by modifying the area ratio of the load transistors.

Abstract translation: 读出放大器的差分输入级具有用于引入预定义滞后的正反馈，其将防止读出放大器的输出的寄生切换，增强抗噪声性。 正反馈通过使用反相放大级来实现，其将在两个开关相中的一个上引入滞后。 读出放大器的阈值可以通过修改负载晶体管的面积比来对称。

公开(公告)号：EP0797208A1

公开(公告)日：1997-09-24

申请号：EP96830128.3

申请日：1996-03-20

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi ,  Barcella, Antonio

IPC: G11C7/00

CPC classification number: G11C7/1006

Abstract: A non-volatile memory device (1) having optimized management of data transmission lines, having the particularity that it comprises at least one bidirectional internal bus (3) that runs from one end of the memory device to the other, one or more source structures (5', 5'') that lie externally and internally to the memory device (1), and timer means (8); the timer means (8) are adapted to time-control the independent and exclusive access of the external and internal source structures (5', 5''), within a same memory cycle, to the internal bus (3) for the transmission of data, controls, and functions, from one end of the memory (1) to the other over the internal bus (3).

Abstract translation: 具有数据传输线路的优化管理的非易失性存储器件（1），其特征在于，它包括从存储器件的一端延伸到另一端的至少一个双向内部总线（3），一个或多个源结构 （5'，5“），其位于存储器件（1）的外部和内部;以及定时器装置（8）; 定时器装置（8）适于对同一存储器周期内的外部和内部源结构（5'，5“）进行时间控制，以内部总线（3）传输 数据，控制和功能，通过内部总线（3）从存储器（1）的一端传输到另一端。

公开(公告)号：EP0788114A1

公开(公告)日：1997-08-06

申请号：EP96830046.7

申请日：1996-02-02

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Fontana, Marco ,  Barcella, Antonio

IPC: G11C11/00 ,  G11C5/14

CPC classification number: G11C5/143

Abstract: A power-on-reset (P.O.R.) circuit producing a power-on-reset (P.O.R.) signal whose an amplitude tracks the voltage on said supply node until it exceeds a certain threshold, has first monitoring and comparing means constituted by at least a nonvolatile memory element having a control gate coupled to said supply node, a first current terminal coupled to a ground node and a second current terminal coupled to a first node which is capacitively coupled to the supply node and second means that include an intrinsically unbalanced bistable circuit, having a node that intrinsically is in a high state at power-on coupled to said first node that intrinsically in a low state at power-on coupled to the input of an output buffer.

Abstract translation: 产生上电复位（POR）信号的上电复位（POR）电路，其幅度跟踪所述供电节点上的电压，直到其超过某个阈值，具有由至少非易失性的第一监视和比较装置构成的第一监视和比较装置 存储元件，其具有耦合到所述电源节点的控制栅极，耦合到接地节点的第一电流端子和耦合到电容耦合到电源节点的第一节点的第二电流端子以及包括本质上不平衡的双稳态电路的第二装置， 具有本身在与上述第一节点通电的高电平状态下处于高电平状态的节点，该节点本质上处于处于与上一个输出缓冲器的输入端相连的上电状态。

公开(公告)号：EP0797146A1

公开(公告)日：1997-09-24

申请号：EP96830127.5

申请日：1996-03-20

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi ,  Barcella, Antonio ,  Rolandi, Paolo ,  Fontana, Marco

IPC: G06F12/00 ,  G06F11/20

CPC classification number: G11C29/70 ,  G11C7/10

Abstract: A data input/output managing device, particularly for non-volatile memories that comprise at least one matrix of memory cells, which has the particularity that it comprises: at least one bidirectional internal bus (1) for the transfer of data from and to the memory; a redundancy management line (2) that is associated with the internal bus (1); means (8) for enabling/disabling the transmission, over the internal bus (1), of the data from the memory toward the outside; means (11) for enabling/disabling access to the internal bus on the part of data whose source is other than the memory matrix, for transmission to the memory matrix; and means (5, 12, 13) for enabling/disabling the connection between the outside of the memory and the redundancy line (2) during the reading of the memory matrix and during its programming.

Abstract translation: 数据输入/输出管理装置，特别是用于非易失性存储器那样包括存储器单元中的至少一个矩阵，它具有特殊性做了它包括：至少一个双向内部总线（1），用于将数据从并到转移的 记忆; 一个冗余管理线（2）并与所述内部总线（1）相关联; 装置（8），用于使能/禁止的传输，通过内部总线（1）从朝向外部存储器中的数据的; 装置（11）用于使在数据源为比存储器矩阵其它，用于传输到存储器矩阵的所述部分/禁止访问内部总线; 和装置（5，12，13），用于使能/禁用存储器矩阵的读出期间和其编程期间存储器的外部和所述冗余线（2）之间的连接。