公开(公告)号：EP0536095B1

公开(公告)日：1998-01-21

申请号：EP92830523.4

申请日：1992-09-24

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi

IPC: G11C7/00 ,  G11C16/06

CPC classification number: G11C16/28 ,  G11C7/14

公开(公告)号：EP0811988A1

公开(公告)日：1997-12-10

申请号：EP96830326.3

申请日：1996-06-06

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi

IPC: G11C29/00 ,  G06F11/00

CPC classification number: G11C29/12 ,  G06F11/006

Abstract: A semiconductor memory device comprising: at least one output data terminal (OB1-OB16,I/O1-I/O16); a matrix of memory cells comprising a plurality of columns (BL) of memory cells; multiplexer means (12) associated to said matrix of memory cells for selectively coupling one of said columns to respective sensing means (13) driving said output data terminal; redundancy columns (RBL) of redundancy memory cells for functionally replacing defective columns in said matrix; first means (RR1-RR4,1) for storing defective addresses of said defective columns in said matrix, for comparing said defective addresses with a current address supplied to the memory device and for selecting a redundancy column when the current address coincides with one of said defective addresses; means for generating an internal timing signal (ATD) activated upon changing of a current address (ADD) supplied to the memory device, the internal timing signal (ATD) remaining activated for a prescribed time starting from the beginning of a read cycle of the memory device. The memory device comprises: redundancy sensing means (10) associated to said redundancy columns (RBL), and redundancy control means (2,3,8,9) supplied by the internal timing signal (ATD) for coupling said output data terminal (OB1-OB16,I/O1-I/O16) of the memory device to said redundancy sensing means (10) in alternative to said sensing means (13) when the current address supplied to the memory device is a defective address, said redundancy control means maintaining the output data terminal of the memory device coupled to said sensing means (13) independently of the current address being a defective address as long as the internal timing signal (ATD) is activated.

Abstract translation: 一种半导体存储器件，包括：至少一个输出数据端子（OB1-OB16，I / O1-I / O16）; 包括存储器单元的多个列（BL）的存储器单元的矩阵; 与所述存储器单元矩阵相关联的多路复用器装置（12），用于选择性地将所述列中的一个耦合到驱动所述输出数据端的相应感测装置（13） 冗余存储单元的冗余列（RBL），用于功能地替换所述矩阵中的有缺陷的列; 用于在所述矩阵中存储所述缺陷列的缺陷地址的第一装置（RR1-RR4,1），用于将所述缺陷地址与提供给存储装置的当前地址进行比较，以及当当前地址与所述存储装置之一一致时选择冗余列 有缺陷的地址; 用于产生在提供给存储装置的当前地址（ADD）改变时激活的内部定时信号（ATD）的装置，从存储器的读取周期的开始开始的规定时间内保持激活的内部定时信号（ATD） 设备。 存储器件包括：与所述冗余列（RBL）相关联的冗余感测装置（10）和由内部定时信号（ATD）提供的冗余控制装置（2,3,8,9），用于将所述输出数据终端 当提供给存储装置的当前地址是缺陷地址时，存储装置的所述冗余感测装置（10）的所述冗余感测装置（10）替代所述感测装置（13），所述冗余度控制装置 只要内部定时信号（ATD）被激活，维持与所述感测装置（13）相连接的存储装置的输出数据终端，独立于作为缺陷地址的当前地址。

公开(公告)号：EP0811918A1

公开(公告)日：1997-12-10

申请号：EP96830324.8

申请日：1996-06-06

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi

IPC: G06F11/20

CPC classification number: G11C29/80 ,  G11C29/808

Abstract: A semiconductor memory device comprises: a plurality of output data terminals (I/OB1-I/OB16,I/O1-I/O16); a matrix of memory cells comprising a plurality of groups (P) of columns (BL) of memory cells, each group of columns being associated to a respective output data terminal; column selection means (4) associated to the matrix of memory cells for selectively coupling one column (BL) for each of the group (P) of columns to a respective sensing means (5) driving the output data terminal; redundancy columns (RBL) of redundancy memory cells for functionally replacing defective columns in the matrix; redundancy column selection means (1) associated to the redundancy columns (RBL) for selectively coupling one redundancy column to a redundancy sensing means (11); defective address storage means (RR,2) for storing defective addresses of the defective columns and identifying codes (OC0-OC3) suitable for identifying the groups (P) of columns wherein the defective columns are located, for comparing the defective addresses with a current address (CADD) supplied to the memory device and for driving the redundancy column selection means for selecting a redundancy column when a current address supplied to the memory device coincides with one of the defective addresses. A shared bus (INTBUS) including a plurality of signal lines (INTBUSi) is provided in the memory device for interconnecting a plurality of circuit blocks (100) of the memory device and for transferring signals between the circuit blocks, the shared bus (INTBUS) being selectively assignable to the circuit blocks in prescribed respective time intervals. The memory device also comprises first bus assignment means (3) associated to the defective address storage means (RR) and second bus assignment means (8) associated to the sensing means (5). The first bus assignment means (3) assign the shared bus (INTBUS), during a first prescribed time interval of a read cycle of the memory device, to the defective address storage means (RR,2) for transferring the identifying code (OC0-OC3) of an addressed defective column to the output data terminals; the second bus assignment means (8) assign the shared bus (INTBUS), during a second prescribed time interval of the read cycle, to the sensing means (5) for transferring output signals of the sensing means (5) to the output data terminals. The transferred identifying code determining an output data terminal associated to the group (P) of columns to which the addressed defective column belongs to be supplied by an output signal of the redundancy sensing means (11) in alternative to an output of the sensing means (5) associated to the group (P) of columns.

Abstract translation: 半导体存储器件包括：多个输出数据端子（I / OB1-I / OB16，I / O1-I / O16）; 包括存储器单元的列（BL）的多个组（P）的存储器单元的矩阵，每组列与相应的输出数据端相关联; 列选择装置（4），其与存储器单元的矩阵相关联，用于选择性地将每个列（P）列的一列（BL）耦合到驱动输出数据端的相应感测装置（5） 冗余存储单元的冗余列（RBL），用于功能地替换矩阵中的有缺陷的列; 与冗余列（RBL）相关联的用于选择性地将一个冗余列耦合到冗余感测装置（11）的冗余列选择装置（1）; 用于存储缺陷列的缺陷地址的缺陷地址存储装置（RR，2）和适合于识别缺陷列所在的列的组（P）的识别代码（OC0-OC3），用于将缺陷地址与电流 提供给存储装置的地址（CADD）和用于驱动冗余列选择装置，用于当提供给存储装置的当前地址与缺陷地址之一重合时选择冗余列。 包括多条信号线（INTBUSi）的共享总线（INTBUS）被提供在存储器件中，用于互连存储器件的多个电路块（100），并用于在电路块之间传送信号，共享总线（INTBUS） 可以在规定的各个时间间隔内选择性地分配给电路块。 存储装置还包括与缺陷地址存储装置（RR）相关联的第一总线分配装置（3）和与感测装置（5）相关联的第二总线分配装置（8）。 第一总线分配装置（3）在存储装置的读取周期的第一规定时间间隔内将共享总线（INTBUS）分配给用于传送识别码（OC0- OC3）到输出数据终端; 第二总线分配装置（8）在读周期的第二规定时间间隔期间将共享总线（INTBUS）分配给感测装置（5），用于将感测装置（5）的输出信号传送到输出数据端 。 所传送的识别码确定与寻址的缺陷列属于的列的组（P）相关联的输出数据终端由冗余感测装置（11）的输出信号提供，以代替感测装置的输出（ 5）与列（P）组相关联。

公开(公告)号：EP0798732A1

公开(公告)日：1997-10-01

申请号：EP96830164.8

申请日：1996-03-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi

IPC: G11C7/06

CPC classification number: G11C7/065 ,  G11C16/28

Abstract: A gain modulated sense amplifier, particularly for memory devices, that comprises a virtual ground latch structure (2) that has two output nodes (OUT-L, OUT-R) and has the particularity that it comprises an equalization transistor (7) of a first polarity that is adapted to equalize the two output nodes (OUT-L, OUT-R) and is connected between a first branch (8) and a second branch (9), in which the output nodes are arranged; the equalization transistor (7) is driven by an equalization signal (EQ) whose slope can be modulated as a function of the conductivity of the memory cell of the memory device involved in the reading operation.

Abstract translation: 一种增益调制读出放大器，特别是用于存储器件的增益调制读出放大器，其包括具有两个输出节点（OUT-L，OUT-R）的虚拟接地锁存结构（2），并且具有特殊性，它包括均衡晶体管 第一极性，其适于使两个输出节点（OUT-L，OUT-R）均衡，并且连接在其中布置有输出节点的第一分支（8）和第二分支（9）之间; 均衡晶体管（7）由均衡信号（EQ）驱动，均衡信号（EQ）的斜率可以作为读取操作中涉及的存储器件的存储单元的电导率的函数进行调制。

公开(公告)号：EP0798642A1

公开(公告)日：1997-10-01

申请号：EP96830167.1

申请日：1996-03-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi

IPC: G06F11/20

CPC classification number: G11C29/84

Abstract: A redundancy management method, particularly for non-volatile memories, having the particularity of comprising the steps of:

-- enabling, as a consequence of the presence of a pulsed read address transition signal of a memory line, and throughout the duration of the pulsed signal, the memory matrix line reading path, and blocking the selection of redundancy lines of the memory; and
-- at the end of the pulsed signal, as a consequence of the absence/presence of a redundancy line read signal, confirming/disabling the selection of the lines of the memory matrix and blocking/releasing the selection of the redundancy lines.

A redundancy management architecture for a memory matrix, adapted to perform the above method, is also described.

Abstract translation: 冗余管理方法，特别是对于非易失性存储器，具有包括如下步骤的特殊性： - 使作为存储器线的脉冲读地址转换信号的存在的结果，并在整个脉冲的持续时间 信号，存储器矩阵行读取路径，并阻断的存储器的冗余行选择; 和 - 在所述脉冲信号的结束，因为不存在的结果/冗余线的存在的读出信号，确认/禁用存储器矩阵的行的选择和阻断/释放冗余线的选择。 冗余管理体系结构的存储器矩阵，angepasst执行上述方法中，如此描述。

公开(公告)号：EP0797209A1

公开(公告)日：1997-09-24

申请号：EP96830129.1

申请日：1996-03-20

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Fontana, Marco ,  Barcella, Antonio

IPC: G11C7/00

CPC classification number: G11C7/1006

Abstract: A non-volatile memory device, having the particularity that it comprises an internal bus (3) for the transmission of data and other information of the memory to output pads (4); timer means (8); and means (5, 5') for enabling/disabling access to the internal bus; the timer means (8) time the internal bus to transmit information signals of the memory device that originate from local auxiliary lines (7) over the internal bus (3) when the bus is in an inactive period during a normal memory data reading cycle; the timer means (8) drive the enabling/disabling means (5, 5') to allow/deny access to the internal bus (3) on the part of the information signals or of the data from or to the memory.

Abstract translation: 一种非易失性存储器件，其特征在于它包括用于将数据和存储器的其它信息传送到输出焊盘（4）的内部总线（3）。 定时器装置（8）; 以及用于启用/禁用访问所述内部总线的装置（5,5'）; 当总线在正常存储器数据读取周期期间处于非活动期间时，定时器装置（8）使内部总线在内部总线（3）上传送来自本地辅助线（7）的存储器件的信息信号; 定时器装置（8）驱动启用/禁用装置（5,5'）以允许/拒绝部分信息信号或来自或向存储器的数据的内部总线（3）的访问。

公开(公告)号：EP0530159B1

公开(公告)日：1997-07-02

申请号：EP92830458.3

申请日：1992-08-27

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi ,  Olivo, Marco

IPC: H03K17/22

CPC classification number: H03K17/223 ,  H03K2217/0036

公开(公告)号：EP0757358A1

公开(公告)日：1997-02-05

申请号：EP95830357.0

申请日：1995-08-04

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pascucci, Luigi

IPC: G11C16/06

CPC classification number: G11C16/26

Abstract: The reading circuit described comprises, for each bit line (BL) of a matrix (11) of memory cells (12), a controllable switching element (To) which can connect the bit line (BL) to a voltage source (V DD ) in response to a control signal applied to a control terminal thereof, a detector stage (16) sensitive to the flow of current through the bit line (BL), and a driving stage (15) comprising two field-effect transistors (TNB, TPB) connected in the inverter configuration with the input of the inverter connected to the bit line (BL) and with the output (CAS) of the inverter connected to the control terminal of the controllable switching element (To). In order to charge the capacitance (C BL ) associated with the bit line rapidly but without causing oscillatory phenomena, the driving stage (15) comprises means (Tnat, Tas) for reducing the gain of the feedback loop formed by the inverter (TNB, TPB) and by the controllable switching element (To).

Abstract translation: 所描述的读取电路对于存储器单元（12）的矩阵（11）的每个位线（BL）包括可控开关元件（To），其可将位线（BL）连接到电压源（VDD） 响应于施加到其控制端的控制信号，对通过位线（BL）的电流流敏感的检测器级（16）以及包括两个场效应晶体管（TNB，TPB）的驱动级（15） 连接在变频器配置中，变频器的输入连接到位线（BL），变频器的输出（CAS）连接到可控开关元件（To）的控制端子。 为了快速地对与位线相关联的电容（CBL）进行充电，但不产生振荡现象，驱动级（15）包括用于降低由逆变器（TNB，TPB）形成的反馈回路的增益的装置（Tnat，Tas） ）和可控开关元件（To）。

公开(公告)号：EP0736876A1

公开(公告)日：1996-10-09

申请号：EP95830133.5

申请日：1995-04-04

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pascucci, Luigi

IPC: G11C16/04 ,  G06F11/20

CPC classification number: G11C29/802 ,  G11C16/0433

Abstract: A coding device including an array of multibit registers, each being composed of a plurality of programmable nonvolatile memory cells connected in an OR configuration to a common sensing line of the register to which a single reading circuit is associated. A first, select/enable bus (SELbus) controls the connection of only one at a time of said programmable memory cells to said common sensing line of each multibit register. To each wire of a second, configuring bus (CODE bus) are connected in common the current terminals of as many programming transistors as the memory cells that compose each register, and to each wire of a third, contingently programming bus (PG bus) are connected the gates of the programming transistors of memory cells of the same order of said registers.

Abstract translation: 一种编码设备，包括多位寄存器阵列，每个寄存器由多个可编程非易失性存储单元组成，所述多个可编程非易失性存储单元以OR配置连接到与单个读取电路相关联的寄存器的公共感测线。 第一选择/启用总线（SELbus）控制每个所述可编程存储单元中的每一个与每个多位寄存器的所述公共感测线的连接。 对于第二个配置总线（CODE总线）的每根导线，共同连接与构成每个寄存器的存储单元以及第三个偶然编程总线（PG总线）的每根导线一样多的编程晶体管的电流端子， 连接所述寄存器的相同顺序的存储单元的编程晶体管的栅极。

公开(公告)号：EP0491105B1

公开(公告)日：1996-05-01

申请号：EP90830583.2

申请日：1990-12-13

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pascucci, Luigi

IPC: G11C16/06 ,  G11C7/00

CPC classification number: G11C16/28 ,  G11C7/14