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    Integrated device with a structure for protection against high electric fields
    2.
    发明公开
    Integrated device with a structure for protection against high electric fields 失效
    具有针对高电场保护的结构的集成器件

    公开(公告)号：EP0714135A1

    公开(公告)日：1996-05-29

    申请号：EP94830530.5

    申请日：1994-11-08

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Contiero, Claudio ,  Depetro, Riccardo

    IPC: H01L29/06 ,  H01L29/78

    CPC classification number: H01L29/7816 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/4238

    Abstract: An integrated device presenting a structure for protection against electric fields. The protection structure is formed by a first region of conducting material (34) connected electrically to the gate/source region (6) of the device and at a first potential, and by a second region of conducting material (35) connected electrically to the drain region (15) of the device and at a second potential differing from the first. The first region of conducting material (34) is comb-shaped, and presents a first number of fingers (32) separated by a number of gaps; and the second region of conducting material (35) presents portions (33) extending at the aforementioned number of gaps and also forming a comb structure, so that the body of semiconductor material (1) of the device sees a protection region formed by a pair of interlocking comb structures and at an intermediate potential between the first and second potentials.

    Mixed technology intergrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage
    3.
    发明公开
    Mixed technology intergrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage 失效
    混合技术集成器件，包含补充LDMOS功率晶体管，CMOS和垂直PNP集成结构，具有增强的耐受能力，可以提供相对高的电源电压

    公开(公告)号：EP0403449A3

    公开(公告)日：1992-07-08

    申请号：EP90830268.0

    申请日：1990-06-14

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Contiero, Claudio ,  Galbiati, Paola ,  Zullino, Lucia

    IPC: H01L27/06 ,  H01L21/82 ,  H01L27/092

    CPC classification number: H01L27/0922 ,  H01L27/0623

    Abstract: Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called "smart power" type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: the drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures. The complementary LDMOS structures may be used either as power structures having a reduced conduction resistance or may be used for realizing CMOS stages capable of operating at a relatively high voltage (of about 20V) thus permitting a direct interfacing with VDMOS power devices without requiring any "level shifting" stages. The whole integrated circuit has less interfacing problems and improved electrical and reliability characteristics.

    An integrated circuit self-protected against reversal of the supply battery polarity
    4.
    发明公开
    An integrated circuit self-protected against reversal of the supply battery polarity 失效
    该集成电路是自保护，以防止供给电池的极性反转。

    公开(公告)号：EP0360991A2

    公开(公告)日：1990-04-04

    申请号：EP89112711.0

    申请日：1989-07-12

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Contiero, Claudio ,  Murari, Bruno

    IPC: H02H11/00 ,  H01L27/02

    CPC classification number: H01L29/7803 ,  H01L27/0218 ,  H01L27/0266 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7809 ,  H01L29/7817 ,  H01L29/7831 ,  H02H11/003 ,  Y10T307/839

    Abstract: An integrated circuit (1) self-protected agianst reversal of the supply battery (2) polarity comprises a first DMOS power transistor (T1) connected with its source electrode (S1) side to an electric load (R1) to be driven toward ground, and a second, protective DMOS transistor (T2) which is connected with its source electrode (S2) side to a positive pole (Vc) of the battery (2) and with its drain electrode (D2) side to the drain electrode (D1) of the first transistor (T1). The first T1) and second (T2) transistors have in common the drain region formed on a single pod (9) in the semiconductor substrate (4).

    Abstract translation: 一种集成电路（1）自保护agianst供给电池的逆转（2）极性包括与它的源极电极（S1）侧连接到在电负载（R1）的第一DMOS功率晶体管（T1）为朝向地面驱动， 和第二保护DMOS晶体管（T2）的所有其与它的源极（S2）侧连接到电池（2），并用它的漏极（D2）侧到漏极电极的正极（VC）（D1） 第一晶体管（T1）的。 第一T1）和第二（T2）的晶体管具有共同形成在半导体衬底（4）的单个盒（9）的漏区。

    VDMOS transistor with improved breakdown characteristics
    6.
    发明公开
    VDMOS transistor with improved breakdown characteristics 失效
    VDMOS-晶体管传递者Durchbruchsspannungscharakteristik。

    公开(公告)号：EP0557253A2

    公开(公告)日：1993-08-25

    申请号：EP93830047.2

    申请日：1993-02-11

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Contiero, Claudio ,  Galbiati, Maria Paola ,  Zullino, Lucia

    IPC: H01L29/772 ,  H01L29/08

    CPC classification number: H01L29/402 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/7809 ,  H01L29/7813 ,  Y10S148/053 ,  Y10S148/126

    Abstract: The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion.
    By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.

    Abstract translation: VDMOS晶体管的击穿电压显着增加，而不会通过将场源隔离层的矩阵与漏极扩散分离的场氧化物带的边缘部分处形成的场隔离扩散的电位相结合来抑制器件的其它电特性 ，到晶体管的源极电位。 这可以通过将外围源电池的体区延伸到面向磁场隔离结构条的每个给定数量的外围电池，直到其与所述场隔离扩散相交为止来实现。 通过将每个给定数量的单元连接一个外围源单元，集成晶体管的整体沟道宽度的实际减小可忽略不计，从而保持功率晶体管的电气特性。

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