公开(公告)号：EP0797165A1

公开(公告)日：1997-09-24

申请号：EP96830137.4

申请日：1996-03-21

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Manganaro, Gabriele ,  Lavorgna, Mario ,  Lo Presti, Matteo ,  Fortuna, Luigi

IPC: G06G7/60

CPC classification number: G06G7/26 ,  G06N3/0635

Abstract: A neural cellular network (10) for implementing a so-called Chua's circuit, and comprising at least first (11), second (12) and third (13) cells having respective first (I111, I121, I131) and second (I112, I122, I132) input terminals and respective state terminals (T11, T12, T13), the first (I111, II121, I131) and second (I112, I122, I132) input terminals being to receive a first (V1) and a second (V2) reference signal, respectively, and the first cell (11), and the second (12) and third (13) cells being of mutually different types.

Abstract translation: 一种用于实现所谓的蔡氏电路的神经细胞网络（10），并且包括至少第一（11），第二（12）和第三（13）小区，其具有相应的第一（I111，I121，I131）和第二（I112， I122，I132）输入端子和各状态端子（T11，T12，T13），第一（I111，II121，I131）和第二（I112，I122，I132）输入端子接收第一（V1）和第二 V2）参考信号，并且第一单元（11）和第二单元（12）和第三单元（13）是相互不同类型的。

公开(公告)号：EP0400748B1

公开(公告)日：1997-08-20

申请号：EP90201351.5

申请日：1990-05-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Taliercio, Michele ,  Lavorgna, Mario ,  Poluzzi, Rinaldo ,  Rizzotto, Gianguido

IPC: G06F17/16

CPC classification number: G06F17/14 ,  G06F17/16

公开(公告)号：EP0400748A3

公开(公告)日：1991-10-23

申请号：EP90201351.5

申请日：1990-05-29

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Taliercio, Michele ,  Lavorgna, Mario ,  Poluzzi, Rinaldo ,  Rizzotto, Gianguido

IPC: G06F15/31

CPC classification number: G06F17/14 ,  G06F17/16

Abstract: The method comprises two time steps of multiplication and accumulation, of which a first step is assigned to the product of the data and of the coefficient matrices and a second step is assigned to the subsequent product by the transposed coefficient matrix. Moreover preferably the data to be transformed and the corresponding coefficients are supplied to a first multiplication step in time succession, possibly after their storage in an appropriate memory. The device for the attainment of said method comprises two multipliers (31, 32) with their corresponding accumulator (33, 30), a RAM-type memory (34) for storing the data to be transformed and the transform coefficients, a multiplexer (39) which receives said data first from the input and then from the memory (34) and arranges them in a time succession for the supply to a first multiplier (31), and a shift register (38) which receives said transform coefficients from the memory (34) and arranges them for the supply to the second multiplier (32).

公开(公告)号：EP0400748A2

公开(公告)日：1990-12-05

申请号：EP90201351.5

申请日：1990-05-29

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Taliercio, Michele ,  Lavorgna, Mario ,  Poluzzi, Rinaldo ,  Rizzotto, Gianguido

IPC: G06F15/31

CPC classification number: G06F17/14 ,  G06F17/16

Abstract: The method comprises two time steps of multiplication and accumulation, of which a first step is assigned to the product of the data and of the coefficient matrices and a second step is assigned to the subsequent product by the transposed coefficient matrix. Moreover preferably the data to be transformed and the corresponding coefficients are supplied to a first multiplication step in time succession, possibly after their storage in an appropriate memory.
The device for the attainment of said method comprises two multipliers (31, 32) with their corresponding accumulator (33, 30), a RAM-type memory (34) for storing the data to be transformed and the transform coefficients, a multiplexer (39) which receives said data first from the input and then from the memory (34) and arranges them in a time succession for the supply to a first multiplier (31), and a shift register (38) which receives said transform coefficients from the memory (34) and arranges them for the supply to the second multiplier (32).

Abstract translation: 该方法包括乘法和累积的两个时间步骤，其中第一步骤被分配给数据和系数矩阵的乘积，并且第二步骤通过转置的系数矩阵分配给后续乘积。 此外，优选地，要被变换的数据和对应的系数可能在它们存储在适当的存储器中之后被提供给第一乘法步骤。 用于实现所述方法的装置包括具有其对应的累加器（33,30）的两个乘法器（31,32），用于存储要变换的数据和变换系数的RAM型存储器（34），多路复用器（39） ），其首先从输入接收所述数据，然后从存储器（34）接收所述数据，并且以时间顺序排列它们以供给第一乘法器（31）;以及移位寄存器（38），其从存储器接收所述变换系数 （34），并且将它们排列供给第二乘法器（32）。