公开(公告)号：EP0833347A1

公开(公告)日：1998-04-01

申请号：EP96830498.0

申请日：1996-09-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Kramer, Alan c/o SGS-Thomson Microelectr. S.r.l. ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Rolandi, Pier Luigi ,  Sabatini, Marco

IPC: G11C27/00

CPC classification number: G11C27/005

Abstract: The programmable reference voltage source (1) includes a nonvolatile memory cell (2), the floating-gate region (3) of which stores electric charges determining a memorized threshold value. The drain terminal (4) of the cell is biased at a constant voltage (D r ), and the source terminal (14) is connected to a constant-current source (21) and to the inverting input of an operational amplifier (21) having the noninverting input connected to a reference voltage (V r ) and the output (10) connected to the gate terminal (8) of the cell (2). By defining the threshold of the cell (2) as the gate voltage (measured with respect to ground) capable of causing the cell (2) to be flown by the current (I s ) set by the current source (22), the output voltage (V o ) of the operational amplifier (21) equals the threshold and may be used as a programmable reference in analog memories.

Abstract translation: 可编程参考电压源（1）包括非易失性存储单元（2），其浮动栅极区域（3）存储确定存储的阈值的电荷。 电池的漏极端子（4）以恒定电压（Dr）被偏置，并且源极端子（14）连接到恒流源（21）和与运算放大器（21）的反相输入端相连， 连接到参考电压（Vr）的非反相输入和连接到单元（2）的栅极端子（8）的输出（10）。 通过将电池（2）的阈值定义为能够使电池（2）由电流源（22）设定的电流（Is）流动的栅极电压（相对于地测量），输出电压 运算放大器（21）的电压（Vo）等于阈值，并且可以用作模拟存储器中的可编程参考。

公开(公告)号：EP0661756B1

公开(公告)日：1997-10-29

申请号：EP93830538.0

申请日：1993-12-31

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Kramer, Alan ,  Sabatini, Marco

IPC: H01L29/788 ,  H01L29/10 ,  G11C27/00

CPC classification number: H01L29/7881 ,  H01L29/1033

公开(公告)号：EP0833267A1

公开(公告)日：1998-04-01

申请号：EP96830492.3

申请日：1996-09-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Kramer, Alan ,  Canegallo, Roberto ,  Rolandi, Pier Luigi ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Sabatini, Marco

IPC: G06G7/60 ,  G06G7/26

CPC classification number: G11C16/0441 ,  G06G7/26 ,  G06N3/0635

Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors (M1,M2) having source and drain terminals which are coupled together and to an injection node (ND), and at least one corresponding pair of generators (G1,G2) of substantially step-like voltage signals (S1,S2) having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors (M1,M2);
the signal generators (G1,G2) being such that the initial value of a first (S1) of the signals is substantially the equal of the final value of a second (S2) of the signals, and that the final value of the first signal (S1) is substantially the equal of the initial value of the second signal (S2).

Abstract translation: 本发明的电荷注入电路包含至少一对浮置栅的MOS晶体管（M1，M2），其耦接在一起，并且至注射节点（ND），其具有源极和漏极端子，以及至少一个对应的一对发电机（G1 的，基本上阶梯状电压信号的G2）（S1，S2），其具有（初始分别耦合到所述的控制端子值和最终值，并且具有输出晶体管M1，M2）; 信号发生器被检查（G1，G2）做了第一（S1）的信号的初始值大致相等的信号的第二（S2）的最终值，并且做的第一信号的最终值 （S1）基本上等于所述第二信号（S2）的初始值的。

公开(公告)号：EP0833454A1

公开(公告)日：1998-04-01

申请号：EP96830491.5

申请日：1996-09-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Kramer, Alan ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Rolandi, Pier Luigi ,  Sabatini, Marco

IPC: H03M1/74

CPC classification number: H03M1/74

Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs (B0,B1,B2,B3) for digital signals, and an output (OUT) for an analog signal, and comprising a charge integration circuit (INT) having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors (M01, M11,M21,M31) corresponding to the plurality of converter inputs, having their source and drain terminals coupled all together and to the input (ND) of the integration circuit (INT), and having control terminals coupleable, under control from the inputs of the plurality, to different references (VCC,GND) of potential having selected fixed values.

Abstract translation: 本发明涉及具有用于数字信号的多个输入（B0，B1，B2，B3）和用于模拟信号的输出（OUT）的数/模转换器，并且包括电荷积分电路（INT） 具有耦合到转换器输出的输入和输出，以及对应于多个转换器输入的多个浮置栅极MOS晶体管（M01，M11，M21，M31），其源极和漏极端子一起耦合到输入端 （INT）的控制端子（ND），并且具有在多个输入端的控制下可控制的控制端子到具有选定的固定值的电位的不同参考（VCC，GND）。

公开(公告)号：EP0833344A1

公开(公告)日：1998-04-01

申请号：EP96830497.2

申请日：1996-09-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Kramer, Alan c/0 SGS-Thomson Microelectr. S.r.l. ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Rolandi, Pier Luigi ,  Sabatini, Marco

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G11C15/046

Abstract: An input structure (1) for associative memories, including an array of elementary cells (2), a number of input lines (20), a number of output lines (30), a number of address lines (40), and a number of enabling lines (50). Each elementary cell (2) is formed by a D type latch (3) having a data input connected to one of the address lines (40) and an enabling input connected to one of the enabling lines (50), and by a switch (4) connected between an input line and an output line, and having a control input connected to the output of a respective latch to selectively connect the respective input line (20) and output line (30) according to the data stored in the latch.

Abstract translation: 一种用于关联存储器的输入结构（1），包括基本单元阵列（2），多个输入线（20），多个输出线（30），多个地址线（40）和数字 的启用线（50）。 每个单元（2）由D型锁存器（3）形成，D型锁存器（3）具有连接到一条地址线（40）的数据输入和连接到一条使能线（50）的使能输入端和一个开关（ 4），其连接在输入线和输出线之间，并且具有连接到相应锁存器的输出的控制输入，以根据存储在锁存器中的数据选择性地连接相应的输入线（20）和输出线（30）。

公开(公告)号：EP0661756A1

公开(公告)日：1995-07-05

申请号：EP93830538.0

申请日：1993-12-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Kramer, Alan ,  Sabatini, Marco

IPC: H01L29/788 ,  H01L29/10 ,  G11C27/00

CPC classification number: H01L29/7881 ,  H01L29/1033

Abstract: Non-volatile memory cell with double level of polycrystalline silicon comprising a source region (38), a drain region (31), a channel region (34) between said source and drain regions, a floating gate (33), and a control gate (32) in which the channel region area extends into two lateral zones beneath the two gates and perpendicular to the source-drain direction.

Abstract translation: 具有双层多晶硅的非易失性存储单元，包括源极区（38），漏极区（31），所述源极和漏极区之间的沟道区（34），浮动栅极（33）和控制栅极 （32），其中沟道区域区域延伸到两个栅极下方并垂直于源极 - 漏极方向的两个侧向区域中。