公开(公告)号：EP0837378A3

公开(公告)日：1998-05-06

申请号：EP97203126.4

申请日：1997-10-08

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Olivieri, Massimiliano ,  Fabbrizio, Vito ,  Guerrieri, Roberto ,  Kramer, Alan

IPC: G05B1/03

CPC classification number: G05D1/0246 ,  G05D2201/0213

Abstract: Method (10), in a system for aiding the guidance of a vehicle, for identifying marking stripes of road lanes comprising the phases of subjecting a road image to a convolution operation (14) with a mask matrix so as to identify discontinuities present in the image, comparing the result with a threshold value (16) and determining (18) a representation of the marking stripes, in which the mask matrix is set in such a way as to eliminate at least partially the discontinuities which do not correspond to the marking stripes.

Abstract translation: 方法（10），在用于辅助车辆引导的系统中，用于识别道路车道的标记条纹，包括使道路图像经受与掩模矩阵的卷积运算（14）的阶段，以识别存在于 图像，将结果与阈值（16）进行比较并确定（18）标记条纹的表示，其中设置掩模矩阵以至少部分消除不对应于标记的不连续性 条纹。

公开(公告)号：EP0774726A1

公开(公告)日：1997-05-21

申请号：EP95830466.9

申请日：1995-11-03

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Chinosi, Mauro ,  Canegallo, Roberto ,  Kramer, Alan ,  Guerrieri, Roberto

IPC: G06G7/60

CPC classification number: G06N3/0635

Abstract: The present invention relates to an analog voltage-signal selector device of the type comprising at least one plurality of comparator circuits (Ci) operating in parallel and each having at least a first and second input terminals and designed to receive respectively an analog voltage-comparison signal (RAMP) and analog voltage signals (Vi) of predetermined value and at least one output terminal for digital voltage signals (Voi).
This selector device 1 also comprises at least one logic circuit (L) having a plurality of input terminals each connected to a corresponding output terminal of the comparator circuits (Ci) and at least one output terminal.
Finally said selector 1 incorporates at least one plurality of latches (Mi) each having at least one input terminal connected to the output terminal of a corresponding comparator circuit (Ci) and at least one drive terminal coupled to the output terminal of the logic circuit (L) with each of said memory circuits (Mi) having at least one output terminal corresponding to an output of the selector.

Abstract translation: 本发明涉及一种模拟电压信号选择器装置，其类型包括至少一个并联工作的多个比较器电路（Ci），并且每个至少具有第一和第二输入端子，并被设计成分别接收模拟电压比较 信号（RAMP）和模拟电压信号（Vi）以及数字电压信号（Voi）的至少一个输出端子。 该选择器装置1还包括具有多个输入端的至少一个逻辑电路（L），每个输入端连接到比较器电路（Ci）的相应输出端和至少一个输出端。 最后，所述选择器1包括至少一个多个锁存器（Mi），每个锁存器具有连接到对应比较器电路（Ci）的输出端的至少一个输入端和耦合到逻辑电路的输出端的至少一个驱动端（ L），其中每个所述存储器电路（Mi）具有对应于选择器的输出的至少一个输出端子。

公开(公告)号：EP0837399A1

公开(公告)日：1998-04-22

申请号：EP96830525.0

申请日：1996-10-15

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Fabbrizio, Vito ,  Kramer, Alan

IPC: G06F15/80

CPC classification number: G06N3/063

Abstract: An electronic device (100) for performing convolution operations comprises shift registers (106-120) for receiving binary input values (122-129) representative of an original matrix, synapses (142) for storing weights correlated with a mask matrix, and neurones (154, 156) for outputting (166, 168) a binary result dependent on the sum of the binary values weighted by the synapses (142), each synapse (142) having a conductance correlated with the weight stored and dependent upon the binary input value and each neurone (154, 156) generating the binary result in dependence on the total conductance of the corresponding synapses (142).

Abstract translation: 用于执行卷积运算的电子设备（100）包括用于接收代表原始矩阵的二进制输入值（122-129）的移位寄存器（106-120），用于存储与掩码矩阵相关的权重的突触（142）和神经元 用于输出（166,168）二进制结果，二进制结果取决于由突触（142）加权的二进制值之和，每个突触（142）具有与存储的权重相关的电导，并且取决于二进制输入值 并且每个神经元（154,156）根据相应突触的总电导（142）产生二进制结果。

公开(公告)号：EP0837378A2

公开(公告)日：1998-04-22

申请号：EP97203126.4

申请日：1997-10-08

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Olivieri, Massimiliano ,  Fabbrizio, Vito ,  Guerrieri, Roberto ,  Kramer, Alan

IPC: G05B1/03

CPC classification number: G05D1/0246 ,  G05D2201/0213

Abstract: Method (10), in a system for aiding the guidance of a vehicle, for identifying marking stripes of road lanes comprising the phases of subjecting a road image to a convolution operation (14) with a mask matrix so as to identify discontinuities present in the image, comparing the result with a threshold value (16) and determining (18) a representation of the marking stripes, in which the mask matrix is set in such a way as to eliminate at least partially the discontinuities which do not correspond to the marking stripes.

Abstract translation: 方法（10）在用于辅助车辆的引导的系统中，用于识别道路车道的标记条纹，其包括用道路图像进行带有掩模矩阵的卷积操作（14）的阶段，以便识别存在于 图像，将结果与阈值（16）进行比较并确定（18）标记条纹的表示，其中掩模矩阵被设置为至少部分地消除不对应于标记的不连续性 条纹。

公开(公告)号：EP0833454A1

公开(公告)日：1998-04-01

申请号：EP96830491.5

申请日：1996-09-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Kramer, Alan ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Rolandi, Pier Luigi ,  Sabatini, Marco

IPC: H03M1/74

CPC classification number: H03M1/74

Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs (B0,B1,B2,B3) for digital signals, and an output (OUT) for an analog signal, and comprising a charge integration circuit (INT) having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors (M01, M11,M21,M31) corresponding to the plurality of converter inputs, having their source and drain terminals coupled all together and to the input (ND) of the integration circuit (INT), and having control terminals coupleable, under control from the inputs of the plurality, to different references (VCC,GND) of potential having selected fixed values.

Abstract translation: 本发明涉及具有用于数字信号的多个输入（B0，B1，B2，B3）和用于模拟信号的输出（OUT）的数/模转换器，并且包括电荷积分电路（INT） 具有耦合到转换器输出的输入和输出，以及对应于多个转换器输入的多个浮置栅极MOS晶体管（M01，M11，M21，M31），其源极和漏极端子一起耦合到输入端 （INT）的控制端子（ND），并且具有在多个输入端的控制下可控制的控制端子到具有选定的固定值的电位的不同参考（VCC，GND）。

公开(公告)号：EP0661756A1

公开(公告)日：1995-07-05

申请号：EP93830538.0

申请日：1993-12-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Kramer, Alan ,  Sabatini, Marco

IPC: H01L29/788 ,  H01L29/10 ,  G11C27/00

CPC classification number: H01L29/7881 ,  H01L29/1033

Abstract: Non-volatile memory cell with double level of polycrystalline silicon comprising a source region (38), a drain region (31), a channel region (34) between said source and drain regions, a floating gate (33), and a control gate (32) in which the channel region area extends into two lateral zones beneath the two gates and perpendicular to the source-drain direction.

Abstract translation: 具有双层多晶硅的非易失性存储单元，包括源极区（38），漏极区（31），所述源极和漏极区之间的沟道区（34），浮动栅极（33）和控制栅极 （32），其中沟道区域区域延伸到两个栅极下方并垂直于源极 - 漏极方向的两个侧向区域中。

公开(公告)号：EP0661756B1

公开(公告)日：1997-10-29

申请号：EP93830538.0

申请日：1993-12-31

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Kramer, Alan ,  Sabatini, Marco

IPC: H01L29/788 ,  H01L29/10 ,  G11C27/00

CPC classification number: H01L29/7881 ,  H01L29/1033

公开(公告)号：EP0768610A1

公开(公告)日：1997-04-16

申请号：EP95830433.9

申请日：1995-10-13

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Fabbrizio, Vito ,  Colli, Gianluca ,  Kramer, Alan

IPC: G06F15/80 ,  G06G7/60

CPC classification number: G06N3/063 ,  G06N3/0635

Abstract: A neural network (1) including a number of synaptic weighting elements (15, 17), and a neuron stage (5); each of the synaptic weighting elements (15, 17) having a respective synaptic input connection (11, 13) supplied with a respective input signal (x 1 , ..., x n ); and the neuron stage (5) having inputs (36, 37) connected to the synaptic weighting elements, and being connected to an output (39) of the neural network (1) supplying a digital output signal (O). The synaptic weighting elements (15, 17) are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage (5) provides for measuring conductance (33-35, 43-45) on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.

Abstract translation: 包括许多突触加权元素（15,17）和神经元阶段（5）的神经网络（1）; 每个突触加权元件（15,17）具有各自的输入信号（x1，...，xn）的突触输入连接（11,13）; 和具有与突触加权元件连接的输入端（36,37）的神经元级（5），并连接到提供数字输出信号（O）的神经网络（1）的输出端（39）。 突触加权元件（15,17）由可编程为不同阈值电压电平的存储器单元形成，使得每个呈现相应的可编程电导; 并且神经元阶段（5）基于通过存储器单元的电流提供测量电导（33-35,43-45），并且基于突触元件的总电导产生二进制输出信号。

公开(公告)号：EP0833267A1

公开(公告)日：1998-04-01

申请号：EP96830492.3

申请日：1996-09-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Kramer, Alan ,  Canegallo, Roberto ,  Rolandi, Pier Luigi ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Sabatini, Marco

IPC: G06G7/60 ,  G06G7/26

CPC classification number: G11C16/0441 ,  G06G7/26 ,  G06N3/0635

Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors (M1,M2) having source and drain terminals which are coupled together and to an injection node (ND), and at least one corresponding pair of generators (G1,G2) of substantially step-like voltage signals (S1,S2) having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors (M1,M2);
the signal generators (G1,G2) being such that the initial value of a first (S1) of the signals is substantially the equal of the final value of a second (S2) of the signals, and that the final value of the first signal (S1) is substantially the equal of the initial value of the second signal (S2).

Abstract translation: 本发明的电荷注入电路包含至少一对浮置栅的MOS晶体管（M1，M2），其耦接在一起，并且至注射节点（ND），其具有源极和漏极端子，以及至少一个对应的一对发电机（G1 的，基本上阶梯状电压信号的G2）（S1，S2），其具有（初始分别耦合到所述的控制端子值和最终值，并且具有输出晶体管M1，M2）; 信号发生器被检查（G1，G2）做了第一（S1）的信号的初始值大致相等的信号的第二（S2）的最终值，并且做的第一信号的最终值 （S1）基本上等于所述第二信号（S2）的初始值的。