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公开(公告)号：EP0479191B1
公开(公告)日：1997-08-13
申请号：EP91116659.3
申请日：1991-09-30
Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.
Inventor： Scarra', Flavio , Morganti, Siro Maurizio , Meroni, Giuseppe
IPC: H03K19/177
CPC classification number: H03K19/17716
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2.发明公开Operational analysis device of the scan path type having a single scanning clock and a single output phase for an integrated circuit 失效具有单个扫描时钟的扫描路径类型的运行分析设备和用于集成电路的单个输出相位
公开(公告)号：EP0482697A3
公开(公告)日：1992-07-22
申请号：EP91202668.9
申请日：1991-10-15
Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.
Inventor： Scarra', Flavio , Gaibotti, Maurizio
IPC: G06F11/26
CPC classification number: G01R31/318552
Abstract: The device comprises a first chain of scanning cells (2) located at the stimulation input of each respective functional block (1) of the integrated circuit and a second chain of scanning cells (3) located at the assessment output of each respective functional block (1) of the integrated circuit. Each cell (2, 3) comprises a master part (M), a slave part (S) and switching means (8, 50) to alternately enable said master (M) and slave parts (S) under the control of respective master clock and slave clock signals coincident with opposite phases of a scanning clock signal (SCK) having a substantially square wave. With each pair of chains of scanning cells (2, 3) there are associated clock generation means (25, 26) to locally obtain said master and slave clocks from said scanning clock (SCK).
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3.发明公开Circuit for the generation of a scanning clock in an operational analysis device of the serial type for an integrated circuit 失效电路，其用于在用于集成电路的操作的串行检查的装置产生采样时钟。
公开(公告)号：EP0491425A2
公开(公告)日：1992-06-24
申请号：EP91203231.5
申请日：1991-12-11
Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.
Inventor： Scarra', Flavio , Gaibotti, Maurizio , Trupia, Giampiero
CPC classification number: G01R31/318552 , G01R31/31727 , H03K5/135
Abstract: The circuit comprises first switching means (11) which receive at input a system clock (XTALIN) normally provided for the operation of the integrated circuit and produce at output a machine clock (CK) normally coincident with the system clock (XTALIN), means for clamping (13) the first switching means (11) which after a firing signal of the serial analysis (ENSH) determine the clamping of the state of the machine clock (CK) and second switching means (14) which receive at input the system clock (XTALIN) and are fired by the firing signal (ENSH) to produce a scanning clock (SCK) which repeats the system clock (XTALIN) in an inverted or non-inverted manner according to the state in which the machine clock (CK) has been clamped.
Abstract translation: 该电路包括第一开关装置（11），其在输入的系统时钟（XTALIN）通常提供用于集成电路的手术接收并在输出端产生一个机器时钟（CK）通常与系统时钟一致（XTALIN）用于 夹紧（13）的第一开关装置（11），该串行分析的点火信号（ENSH）确定性矿机器时钟（CK）的状态的夹紧和第二开关装置（14），其在输入的系统时钟接收后 （XTALIN）和由所述发射信号（ENSH）以产生扫描时钟（SCK）进行烧成其中在倒置或不倒置的方式雅丁重复系统时钟（XTALIN），其中所述机器时钟（CK）具有状态 被夹紧。
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4.发明授权Operational analysis device of the scan path type having a single scanning clock and a single output phase for an integrated circuit 失效从Abtastpfadtyp操作分析装置仅具有一个采样时钟和唯一的一个输出相对于集成电路
公开(公告)号：EP0482697B1
公开(公告)日：1998-07-08
申请号：EP91202668.9
申请日：1991-10-15
Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.
Inventor： Scarra', Flavio , Gaibotti, Maurizio
IPC: G06F11/26
CPC classification number: G01R31/318552
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公开(公告)号：EP0486444A3
公开(公告)日：1993-06-02
申请号：EP91830496.5
申请日：1991-11-13
Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.
Inventor： Natale, Virginia , Petrosino, Gianluca , Scarra', Flavio
IPC: H01L27/115 , G11C16/06 , H01L23/522
CPC classification number: H01L27/115
Abstract: Each common source region of the cells of a row of a FLASH-EPROM matrix may be segmented and each segment is individually connected to a secondary source line patterned in a second level metal layer by means of a plurality of contacts between each common source region and patterned portions of a first level metal and through as many interconnection vias between the latter patterned portions of metal 1 and the relative secondary source line patterned in metal 2. The secondary source lines are brought out of the matrix orthogonally to the bit lines and may be connected to a dedicated selection circuitry, thus permitting the erasing by groups or banks of cells of the FLASH-EPROM memory.
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Patent Agency Ranking6.发明公开Operational analysis device of the scan path type having a single scanning clock and a single output phase for an integrated circuit 失效从Abtastpfadtyp操作分析装置仅具有一个采样时钟和唯一一个用于集成电路的输出相位。
公开(公告)号：EP0482697A2
公开(公告)日：1992-04-29
申请号：EP91202668.9
申请日：1991-10-15
Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.
Inventor： Scarra', Flavio , Gaibotti, Maurizio
IPC: G06F11/26
CPC classification number: G01R31/318552
Abstract: The device comprises a first chain of scanning cells (2) located at the stimulation input of each respective functional block (1) of the integrated circuit and a second chain of scanning cells (3) located at the assessment output of each respective functional block (1) of the integrated circuit. Each cell (2, 3) comprises a master part (M), a slave part (S) and switching means (8, 50) to alternately enable said master (M) and slave parts (S) under the control of respective master clock and slave clock signals coincident with opposite phases of a scanning clock signal (SCK) having a substantially square wave. With each pair of chains of scanning cells (2, 3) there are associated clock generation means (25, 26) to locally obtain said master and slave clocks from said scanning clock (SCK).
Abstract translation: 该装置包括：扫描单元的第一链（2）位于每个respectivement功能块的刺激输入（1）所述集成电路和扫描单元的第二链的（3）位于每个respectivement功能块的评估输出（ 集成电路的1）。 每个小区（2，3）包括主部（M），从动部分（S）和开关装置（8，50），以交替地使respectivement主时钟的控制下，所述主（M）和从属份（S） 及合并具有大致方波的扫描时钟信号（SCK）的相反相位的从时钟信号。 与每对扫描单元的链的（2,3）有相关时钟产生装置（25，26），以获得从所述扫描时钟（SCK）本地所述主时钟和从时钟。
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7.发明公开Data transfer in DMA mode during a wake up phase of a microprocessor in a wait for interrupt condition for reducing power consumption 失效在DMA模式下的数据传输用于Erwachungsphase由微处理器在等待状态中，用于中断以降低功率消耗。
公开(公告)号：EP0458756A1
公开(公告)日：1991-11-27
申请号：EP91830166.4
申请日：1991-04-23
Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.
Inventor： Scarra', Flavio
CPC classification number: G06F1/3215 , G06F13/285
Abstract: In a microprocessor system provided with integrated DMA channels for transferring data from peripherals associated with the microprocessor and internal and/or external data storage physical resources of the microprocessor system and viceversa, a request for a data transfer in DMA mode is accepted also during a wait for interrupt (WFI) state of the microprocessor, whose CPU is momentarily restored to full operativity for the time necessary for completing the data transfer in DMA mode before being returned to the "power down" condition of a wait for interrupt state. Power consumption is reduced and data transactions are performed swiftly.
Abstract translation: 在从与所述微处理器系统，反之亦然的微处理器和内部和/或外部数据存储的物理资源相关联的外围设备设置有集成的DMA通道用于传递环数据的微处理器系统中，用于在DMA模式下的数据传送的请求时的等待期间，接受这样 用于微处理器，谁的CPU被瞬间完全恢复为操作性所必需的时间被返回到“断电”一个等待中断状态的条件之前完成在DMA模式下的数据传输的中断（WFI）状态。 降低功耗和数据处理，迅速执行。
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8.发明授权Circuit for the generation of a scanning clock in an operational analysis device of the serial type for an integrated circuit 失效电路，其用于在装置中产生采样时钟用于集成电路的操作的串行检查
公开(公告)号：EP0491425B1
公开(公告)日：1997-03-19
申请号：EP91203231.5
申请日：1991-12-11
Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.
Inventor： Scarra', Flavio , Gaibotti, Maurizio , Trupia, Giampiero
CPC classification number: G01R31/318552 , G01R31/31727 , H03K5/135
Abstract: The circuit comprises first switching means (11) which receive at input a system clock (XTALIN) normally provided for the operation of the integrated circuit and produce at output a machine clock (CK) normally coincident with the system clock (XTALIN), means for clamping (13) the first switching means (11) which after a firing signal of the serial analysis (ENSH) determine the clamping of the state of the machine clock (CK) and second switching means (14) which receive at input the system clock (XTALIN) and are fired by the firing signal (ENSH) to produce a scanning clock (SCK) which repeats the system clock (XTALIN) in an inverted or non-inverted manner according to the state in which the machine clock (CK) has been clamped.
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9.发明公开Monostabilized dynamic programmable logic array (PLA) in CMOS technology 失效CMOS技术中的可修改动态可编程逻辑阵列（PLA）
公开(公告)号：EP0479191A3
公开(公告)日：1992-07-08
申请号：EP91116659.3
申请日：1991-09-30
Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.
Inventor： Scarra', Flavio , Morganti, Siro Maurizio , Meroni, Giuseppe
IPC: H03K19/177
CPC classification number: H03K19/17716
Abstract: The circuit includes an input register (RI) and an output register (RU); an AND plane formed by vertical lines (Y), which are controlled by the input register, and by horizontal lines (L) which include normally-off transistors (TA) which are arranged in series between the power supply and the ground and are controlled by respective vertical lines of the AND plane; an OR plane formed by horizontal lines (S), which are controlled by the horizontal lines of the AND plane, by vertical lines (U) between the power supply and the output register, and by normally-off transistors (TO) which can be connected between the ground and selected vertical lines and are controlled by respective horizontal lines of the OR plane. According to the invention, the connections toward the ground and toward the power supply of the horizontal lines of the AND plane are respectively constituted by normally-off transistors (TV) and by normally-on transistors (TP) which can be controlled by a first clock signal (CK1 ∼ ); the connections between the horizontal lines of the OR plane and, furthermore, the power supply are constituted by respective normally-on transistors (TR) which can be controlled by a second clock signal (CK2 ∼ ), and the connections between the horizontal lines of the AND plane and the horizontal lines of the OR plane are constituted by respective pairs of normally-on transistors (TB) and normally-off transistors (TC) arranged in series between the power supply and the ground. In each pair, the normally-on transistor is controlled by the horizontal line of the AND plane, the normally-off transistor is controlled by a third clock signal (CK2), and the horizontal line of the OR plane is connected to the node between the two transistors of the pair.
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10.发明公开Double metal, bank erasable, flash-EPROM memory 失效AggregatslöschbareFlash-EPROM-Anordnung mit zwei Metallschichten。
公开(公告)号：EP0486444A2
公开(公告)日：1992-05-20
申请号：EP91830496.5
申请日：1991-11-13
Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.
Inventor： Natale, Virginia , Petrosino, Gianluca , Scarra', Flavio
IPC: H01L27/115 , G11C16/06 , H01L23/522
CPC classification number: H01L27/115
Abstract: Each common source region of the cells of a row of a FLASH-EPROM matrix may be segmented and each segment is individually connected to a secondary source line patterned in a second level metal layer by means of a plurality of contacts between each common source region and patterned portions of a first level metal and through as many interconnection vias between the latter patterned portions of metal 1 and the relative secondary source line patterned in metal 2. The secondary source lines are brought out of the matrix orthogonally to the bit lines and may be connected to a dedicated selection circuitry, thus permitting the erasing by groups or banks of cells of the FLASH-EPROM memory.
Abstract translation: FLASH-EPROM矩阵的行的单元的每个公共源区可以被分割，并且每个段通过每个公共源区和多个第二级金属层之间的多个接触单独地连接到图案化在第二级金属层中的次级源极线 第一级金属的图案化部分以及通过在金属1的后面的图案化部分和在金属2中图案化的相对次级源极线之间的尽可能多的互连通孔。次级源极线从矩阵正交地离开位线，并且可以是 连接到专用选择电路，从而允许FLASH-EPROM存储器的单元的组或块的擦除。
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