公开(公告)号：EP0479191A2

公开(公告)日：1992-04-08

申请号：EP91116659.3

申请日：1991-09-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Scarra', Flavio ,  Morganti, Siro Maurizio ,  Meroni, Giuseppe

IPC: H03K19/177

CPC classification number: H03K19/17716

Abstract: The circuit includes an input register (RI) and an output register (RU); an AND plane formed by vertical lines (Y), which are controlled by the input register, and by horizontal lines (L) which include normally-off transistors (TA) which are arranged in series between the power supply and the ground and are controlled by respective vertical lines of the AND plane; an OR plane formed by horizontal lines (S), which are controlled by the horizontal lines of the AND plane, by vertical lines (U) between the power supply and the output register, and by normally-off transistors (TO) which can be connected between the ground and selected vertical lines and are controlled by respective horizontal lines of the OR plane. According to the invention, the connections toward the ground and toward the power supply of the horizontal lines of the AND plane are respectively constituted by normally-off transistors (TV) and by normally-on transistors (TP) which can be controlled by a first clock signal (CK1 ∼ ); the connections between the horizontal lines of the OR plane and, furthermore, the power supply are constituted by respective normally-on transistors (TR) which can be controlled by a second clock signal (CK2 ∼ ), and the connections between the horizontal lines of the AND plane and the horizontal lines of the OR plane are constituted by respective pairs of normally-on transistors (TB) and normally-off transistors (TC) arranged in series between the power supply and the ground. In each pair, the normally-on transistor is controlled by the horizontal line of the AND plane, the normally-off transistor is controlled by a third clock signal (CK2), and the horizontal line of the OR plane is connected to the node between the two transistors of the pair.

Abstract translation: 该电路包括输入寄存器（RI）和输出寄存器（RU）; 由输入寄存器控制的垂直线（Y）和由电源和地之间串联布置的常关晶体管（TA）的水平线（L）形成的AND平面被控制 通过AND平面的相应垂直线; 由AND面平面的水平线由电源和输出寄存器之间的垂直线（U）以及常闭晶体管（TO）形成的由水平线（S）形成的OR平面，其可以是 连接在地面和选定的垂直线之间，并由OR平面的相应水平线控制。 根据本发明，与平面的水平线的接地和朝向电源的连接分别由常闭晶体管（TV）和正常导通的晶体管（TP）构成，其可以由第一 时钟信号（CK1 ）; OR平面的水平线之间的连接以及另外的电源由可由第二时钟信号（CK2 ）控制的相应的常通晶体管（TR）构成，并且水平 AND平面的线和OR平面的水平线由在电源和地之间串联布置的各对正常导通晶体管（TB）和常关断晶体管（TC）构成。 在每对中，常通晶体管由AND平面的水平线控制，常关晶体管由第三时钟信号（CK2）控制，OR平面的水平线连接到 该对的两个晶体管。

公开(公告)号：EP0479191B1

公开(公告)日：1997-08-13

申请号：EP91116659.3

申请日：1991-09-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Scarra', Flavio ,  Morganti, Siro Maurizio ,  Meroni, Giuseppe

IPC: H03K19/177

CPC classification number: H03K19/17716

公开(公告)号：EP0575688A3

公开(公告)日：1994-03-16

申请号：EP92830552.3

申请日：1992-10-01

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Ghio, Emilio Giambattista ,  Meroni, Giuseppe ,  Re, Danilo ,  Baldi, Livio

IPC: H01L27/112 ,  H01L21/82

CPC classification number: H01L27/11266 ,  H01L27/112

Abstract: ROM memories made in MOS or CMOS technology with LDD cells may be programmed advantageously in a relatively advanced stage of fabrication by decoupling an already formed drain region from the channel region of cells to be permanently made nonconductive (programmed) by implanting a dopant in an amount sufficient to invert the type of conductivity in a portion of the drain region adjacent to the channel region. In CMOS processes, the programming mask may be a purposely modified mask commonly used for implanting source/drain regions of transistors of a certain type of conductivity. By using high-energy implantation and a dedicated mask, the programming may be effected at even later stages of the fabrication process.

Abstract translation: 采用MOS或CMOS技术制造的具有LDD单元的ROM存储器可以有利地在相对高级的制造阶段通过将已形成的漏极区与单元的沟道区解耦以通过注入一定量的掺杂剂而永久地形成非导电（编程） 足以反转与沟道区相邻的漏极区的一部分中的导电类型。 在CMOS工艺中，编程掩模可以是通常用于注入某种导电类型的晶体管的源极/漏极区的有意修改的掩模。 通过使用高能量注入和专用掩模，编程可以在制造过程的甚至更晚的阶段进行。

公开(公告)号：EP0575688B1

公开(公告)日：1998-05-27

申请号：EP92830552.3

申请日：1992-10-01

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Ghio, Emilio Giambattista ,  Meroni, Giuseppe ,  Re, Danilo ,  Baldi, Livio

IPC: H01L27/112 ,  H01L21/8246

CPC classification number: H01L27/11266 ,  H01L27/112

公开(公告)号：EP0575688A2

公开(公告)日：1993-12-29

申请号：EP92830552.3

申请日：1992-10-01

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Ghio, Emilio Giambattista ,  Meroni, Giuseppe ,  Re, Danilo ,  Baldi, Livio

IPC: H01L27/112 ,  H01L21/82

CPC classification number: H01L27/11266 ,  H01L27/112

Abstract: ROM memories made in MOS or CMOS technology with LDD cells may be programmed advantageously in a relatively advanced stage of fabrication by decoupling an already formed drain region from the channel region of cells to be permanently made nonconductive (programmed) by implanting a dopant in an amount sufficient to invert the type of conductivity in a portion of the drain region adjacent to the channel region. In CMOS processes, the programming mask may be a purposely modified mask commonly used for implanting source/drain regions of transistors of a certain type of conductivity. By using high-energy implantation and a dedicated mask, the programming may be effected at even later stages of the fabrication process.

Abstract translation: 在具有LDD单元的MOS或CMOS技术中制造的ROM存储器可以通过将已经形成的漏极区域与单元的沟道区域去耦合而被有利地编程在相对较先进的制造阶段，以通过将量子点 足以反转与沟道区相邻的漏极区的一部分中的导电性的类型。 在CMOS工艺中，编程掩模可以是通常用于注入某种导电性晶体管的源极/漏极区域的有意修改的掩模。 通过使用高能量注入和专用掩模，编程可以在制造过程的甚至更晚阶段进行。

公开(公告)号：EP0479191A3

公开(公告)日：1992-07-08

申请号：EP91116659.3

申请日：1991-09-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Scarra', Flavio ,  Morganti, Siro Maurizio ,  Meroni, Giuseppe

IPC: H03K19/177

CPC classification number: H03K19/17716

Abstract: The circuit includes an input register (RI) and an output register (RU); an AND plane formed by vertical lines (Y), which are controlled by the input register, and by horizontal lines (L) which include normally-off transistors (TA) which are arranged in series between the power supply and the ground and are controlled by respective vertical lines of the AND plane; an OR plane formed by horizontal lines (S), which are controlled by the horizontal lines of the AND plane, by vertical lines (U) between the power supply and the output register, and by normally-off transistors (TO) which can be connected between the ground and selected vertical lines and are controlled by respective horizontal lines of the OR plane. According to the invention, the connections toward the ground and toward the power supply of the horizontal lines of the AND plane are respectively constituted by normally-off transistors (TV) and by normally-on transistors (TP) which can be controlled by a first clock signal (CK1 ∼ ); the connections between the horizontal lines of the OR plane and, furthermore, the power supply are constituted by respective normally-on transistors (TR) which can be controlled by a second clock signal (CK2 ∼ ), and the connections between the horizontal lines of the AND plane and the horizontal lines of the OR plane are constituted by respective pairs of normally-on transistors (TB) and normally-off transistors (TC) arranged in series between the power supply and the ground. In each pair, the normally-on transistor is controlled by the horizontal line of the AND plane, the normally-off transistor is controlled by a third clock signal (CK2), and the horizontal line of the OR plane is connected to the node between the two transistors of the pair.