公开(公告)号：EP0757355A1

公开(公告)日：1997-02-05

申请号：EP95830347.1

申请日：1995-07-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Calligaro, Cristiano ,  Daniele, Vincenzo ,  Gastaldi, Roberto ,  Manstretta, Alessandro ,  Telecco, Nicola ,  Torelli, Guido

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C2211/5632 ,  G11C2211/5633

Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2 n (n > = 2) different programming levels, provides for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a discrete set of m distinct cell current values (IC0-IC15), each cell current value (IC0-IC15) corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current (IC) with a prescribed number of reference currents (IR1,IR2,IR3) having values comprised between a minimum value and a maximum value of said discrete set of m cell current values (IC0-IC15) and dividing said discrete set of m cell current values (IC0-IC15) in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current (IC) belongs; repeating step a) for the sub-set of cell current values to which the cell current (IC) belongs, until the sub-set of cell current values to which the cell current (IC) belongs comprises only one cell current value, which is the value of the current (IC) of the memory cell (MC) to be sensed.

Abstract translation: 这可能需要m的多元性中的一个编程电平，用于感测多电平非易失性存储器单元的方法= 2 （N> = 2）不同的编程的水平，提供了一种用于偏置的存储单元（MC）被感测到的 在预定条件下，所以没有存储器单元（MC）汇的单元电流（IC）与值属于一组离散的m个不同的单元电流值的（IC 0-IC15），每个单元的电流值（IC 0-IC15）对应 与所述编程水平之一。 所述sensingmethod因此提供用于：同时单元电流（IC）与参考电流（IR1，IR2，IR3）的最小值和所述离散组m个单元电流值的最大值之间由具有值的规定数量的比较（ IC 0-IC15）和将所述离散组m个单元电流值的（IC 0-IC15）（在子集的单元电流值的复数，用于确定性采矿子集小区的电流值，以该单元电流IC）属于 ; 重复步骤a）用于单元电流值的子集到的电池电流（IC）所属直到单元电流值的子集到的电池电流（IC）属于仅包括一个单元电流值，在所有其 要被感测的存储单元（MC）的电流（IC）的值。

公开(公告)号：EP0569658A1

公开(公告)日：1993-11-18

申请号：EP92830230.6

申请日：1992-05-15

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Marchesi, Gianmarco ,  Torelli, Guido

IPC: H03L7/24 ,  H03K3/03

CPC classification number: H03K3/0315 ,  H03L7/24

Abstract: A non-overlapping phase, signal generator (1) comprises first and second loop oscillators (O1,O2) including cascaded inverters. Defined in each cascade of inverters are first and second circuit nodes between the inverters. Between the first node (2) of the first oscillator and the second node (3A) of the second oscillator, there is connected a transistor having a control terminal connected to the first node of the second oscillator. Connected between the first node (2A) of the second oscillator (O2) and the second node (3) of the first oscillator is a transistor having a control terminal connected to the first node of the first oscillator (O1).

Abstract translation: 非重叠相位信号发生器（1）包括包括级联反相器的第一和第二环路振荡器（O1，O2）。 在每个级联的逆变器中定义了逆变器之间的第一和第二电路节点。 在第一振荡器的第一节点（2）和第二振荡器的第二节点（3A）之间，连接有具有连接到第二振荡器的第一节点的控制端子的晶体管。 连接在第二振荡器（O2）的第一节点（2A）和第一振荡器的第二节点（3）之间的是具有连接到第一振荡器（O1）的第一节点的控制端子的晶体管。

公开(公告)号：EP0492506A2

公开(公告)日：1992-07-01

申请号：EP91121952.5

申请日：1991-12-20

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Maloberti, Franco ,  Portaluri, Salvatore ,  Torelli, Guido

IPC: H03K19/003

CPC classification number: H03K17/163 ,  H03K19/00361

Abstract: A fast capacitive - load driving circuit for driving output nodes on an integrated circuit. This circuit reduces noise interference caused by parasitic inductance by lowering the inductance voltage on the power supply lines during the switching process. This invention includes a voltage ramp (B1), a voltage-to-current converter (B2), and an output buffer having at least one pull-down transistor (MD). A further embodiment includes an output buffer possessing a pull-down (MD) and a pull-up transistor (MU).

Abstract translation: 一种快速电容 - 负载驱动电路，用于在集成电路驱动输出节点。 该电路通过降低在切换过程中降低对电源线的电感电压由寄生电感引起的噪声的干扰。 本发明包括一个电压斜坡，一个电压 - 电流转换器，以及具有至少一个下拉晶体管的输出缓冲区。 另一个实施例包括在输出缓冲器波塞唱下拉和上拉晶体管。

公开(公告)号：EP0320471A2

公开(公告)日：1989-06-14

申请号：EP88830530.7

申请日：1988-12-09

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Devecchi, Daniele ,  Torelli, Guido

IPC: H03F3/45

CPC classification number: H03F3/45941 ,  H03F3/45475 ,  H03F2203/45424

Abstract: In a chain of fully differential amplifiers, comprising at least two cascaded amplifiers, the stabilization of the output common mode voltage of an amplifier is implemented by sensing the value of such a voltage by means of a dedi­cated terminal connected to a circuit node corresponding to the sources connected in common of the input differen­tial pair of transistors of an amplifier which follows in the chain of cascaded amplifiers. Such a voltage is compa­red with a reference voltage to which, by means of a le­vel shifting circuit, a voltage equivalent to the thre­shold voltage of the said transistors forming said input pair is subtracted thus obtaining an error signal of the out­put common voltage of said amplifier to be stabilized which may be applied to a dedicated control terminal thereof. The system of the invention provides for the sensing of the output common mode voltage without loading the ouputs of the amplifier to be stabilized and it is more easily implemen­ted than known systems.

Abstract translation: 在包括至少两个级联放大器的全差分放大器链中，放大器的输出共模电压的稳定通过利用连接到对应于电路的电路节点的专用终端来感测这种电压的值来实现 连接在级联放大器链中的放大器的输入差分对的晶体管的源极。 将这样的电压与参考电压进行比较，借此通过电平移位电路减去与形成所述输入对的所述晶体管的阈值电压相当的电压，从而获得所述放大器的输出公共电压的误差信号 可以被施加到其专用控制端子。 本发明的系统提供对输出共模电压的感测，而不加载要稳定的放大器的输出，并且比已知系统更容易实现。

公开(公告)号：EP0646924A1

公开(公告)日：1995-04-05

申请号：EP93830403.7

申请日：1993-09-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Calligaro, Cristiano ,  Gastaldi, Roberto ,  Malcovati, Piero ,  Torelli, Guido

IPC: G11C5/00 ,  H02M3/07

CPC classification number: H02M3/07 ,  G11C5/145

Abstract: A circuit for generating positive and negative boosted voltages, comprising first (El-pos) and second (El-neg) voltage booster circuits, respectively for positive and negative voltages, which have output terminals interconnected at a common node (N).
It comprises two tristate logic gate circuits for coupling said voltage booster circuits to a positive supply voltage generator (Vdd,GND) and additional tristate logic gate circuits for driving the phases of charge pump circuits incorporated to the booster circuits.
This voltage generating circuit may be integrated in single-well CMOS technology.

Abstract translation: 一种用于生成正和负电路升压的电压，其包括第一发光（EL-POS）和第二致发光（EL-NEG）电压升压电路，用于分别正和负电压，其具有在一个共同的节点（N）相互连接的输出端子。 它包括两个三态逻辑门电路，用于耦合所述电压升压电路到正电源电压发生器（VDD，GND）和另外的三态逻辑门电路，用于驱动的​​方式并入到升压电路的电荷泵电路的相位。 该电压产生电路可以被集成在单阱CMOS技术。

公开(公告)号：EP0320471B1

公开(公告)日：1994-04-13

申请号：EP88830530.7

申请日：1988-12-09

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Devecchi, Daniele ,  Torelli, Guido

IPC: H03F3/45

CPC classification number: H03F3/45941 ,  H03F3/45475 ,  H03F2203/45424

公开(公告)号：EP0569658B1

公开(公告)日：1998-08-12

申请号：EP92830230.6

申请日：1992-05-15

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Marchesi, Gianmarco ,  Torelli, Guido

IPC: H03L7/24 ,  H03K3/03

CPC classification number: H03K3/0315 ,  H03L7/24

公开(公告)号：EP0492506B1

公开(公告)日：1997-04-02

申请号：EP91121952.5

申请日：1991-12-20

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Maloberti, Franco ,  Portaluri, Salvatore ,  Torelli, Guido

IPC: H03K19/003

CPC classification number: H03K17/163 ,  H03K19/00361

公开(公告)号：EP0576774A1

公开(公告)日：1994-01-05

申请号：EP92830340.3

申请日：1992-06-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Flocchi, Carlo ,  Torelli, Guido

IPC: G11C16/06

CPC classification number: G11C16/30

Abstract: A voltage regulator for electrically programmable, non-volatile memory devices, having an output terminal connected to a power supply line for programming the state of at least one memory element through at least one selection circuit means (MW,MB) and comprising at least first (R1) and second (R2) resistive elements connected between first and second terminals of a voltage supply. The regulator further comprises at least a second circuit means (MWd,MBd) being the homolog of the selection circuit means for programming the memory element, said second circuit means being connected serially to the resistive elements (R1,R2) across the two terminals of the voltage supply. Also provided is at least one controlled current generator (G1,G2) connected between one of the two voltage supply terminals and a linking node to one of the resistive elements and an operational amplifier (A) whose non-inverting (+) input is connected to a linking node to at least one of the resistive elements and whose output terminal is the output terminal of the regulator.

Abstract translation: 一种用于电可编程非易失性存储器件的电压调节器，其具有连接到电源线的输出端，用于通过至少一个选择电路装置（MW，MB）对至少一个存储元件的状态进行编程，并且至少包括第一 （R1）和第二（R2）电阻元件，其连接在电压源的第一和第二端子之间。 调节器还包括至少第二电路装置（MWd，MBd），其是用于对存储元件进行编程的选择电路装置的同源物，所述第二电路装置串联连接到跨过两个端子的电阻元件（R1，R2） 电压供应。 还提供了连接在两个电压源端子之一和与电阻元件中的一个的连接节点的至少一个受控电流发生器（G1，G2）和其非反相（+）输入端连接的运算放大器（A） 到至少一个电阻元件的连接节点，并且其输出端子是调节器的输出端子。

公开(公告)号：EP0335102A3

公开(公告)日：1990-07-18

申请号：EP89102973.8

申请日：1989-02-21

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Devecchi, Daniele ,  Torelli, Guido

IPC: H03F3/345

CPC classification number: H03F3/345

Abstract: A first N-channel transistor (M1) and a second N-­channel transistor (M2) are cascode connected and the source electrode of the first transistor is connected to the ground; a third P-channel transistor (M3) and a fourth P-channel transistor (M4) are also cascode connected, and the source of the fourth transistor is connected to a supply voltage; the drains of the second and third transistors (M2, M3) are mutually connected to act as output terminal. According to the invention, the absolute values of the threshold voltages of the second and third transistors are lower than the threshold voltages of the first and fourth transistors, and the gates of the first and second transistors are furthermore mutually connected to act as input terminal for a voltage signal, while the gates of said third and fourth transistors are mutually connected to act as input terminal for a bias voltage.