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    Decoder
    1.
    发明公开
    Decoder 失效
    解码器

    公开(公告)号：EP0442220A3

    公开(公告)日：1992-12-09

    申请号：EP90314121.6

    申请日：1990-12-21

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Forsyth, Richard Matthew

    IPC: G06F1/02

    CPC classification number: G06F7/535 ,  G06F1/02 ,  G06F7/60 ,  G06F2207/5352

    Abstract: A decoder has a plurality of outputs (R o -R N ) each associated with a particular output value and is arranged to add together two binary numbers (A, B) and to select one of said outputs in dependence on the result of said sum. The decoder comprises a plurality of logic circuits each arranged to receive respective bits of both first and second binary numbers to be added together said logic circuits being arranged to provide, for each output value, a respective result in dependence on the logic states of said bits and on the logic states of respective bits of binary numbers representing the particular output value of the decoder; and logic means for determining when a predetermined condition is satisfied by all the results of the logic circuits associated with an output value of the decoder, whereby that output value is selected. In the preferred embodiment, for adding together two n bit numbers, there are n+l logic circuits (L), each arranged to receive the ith and i-lth bits (Ai, Ai-l, Bi, Bi-l) of first and second n bit numbers, and each arranged to provide an output in dependence on the logic states of said bits and on the logic states of the ith and i-lth bits (Qi, Qi-l) of respective binary numbers which are the ones complement of binary numbers R o ...R N representing each respective output value of the decoder in accordance with the following expression: Ai ⊕ Bi ⊕ Qi ⊕ (Ai-l-Bi-l + Qi-l. (Ai-l + Bi-l)). The predetermined condition is then satisfied when the above expression has a logic value of ONE. A plurality of AND gates are associated respectively with the outputs of the decoder and are each arranged to receive the outputs of the n+l logic circuits for each output value of the decoder. The decoder performs addition and decoding in one step.

    Decoder
    2.
    发明公开
    Decoder 失效
    Dekodierer。

    公开(公告)号：EP0442220A2

    公开(公告)日：1991-08-21

    申请号：EP90314121.6

    申请日：1990-12-21

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Forsyth, Richard Matthew

    IPC: G06F1/02

    CPC classification number: G06F7/535 ,  G06F1/02 ,  G06F7/60 ,  G06F2207/5352

    Abstract: A decoder has a plurality of outputs (R o -R N ) each associated with a particular output value and is arranged to add together two binary numbers (A, B) and to select one of said outputs in dependence on the result of said sum. The decoder comprises a plurality of logic circuits each arranged to receive respective bits of both first and second binary numbers to be added together said logic circuits being arranged to provide, for each output value, a respective result in dependence on the logic states of said bits and on the logic states of respective bits of binary numbers representing the particular output value of the decoder; and logic means for determining when a predetermined condition is satisfied by all the results of the logic circuits associated with an output value of the decoder, whereby that output value is selected.
    In the preferred embodiment, for adding together two n bit numbers, there are n+l logic circuits (L), each arranged to receive the ith and i-lth bits (Ai, Ai-l, Bi, Bi-l) of first and second n bit numbers, and each arranged to provide an output in dependence on the logic states of said bits and on the logic states of the ith and i-lth bits (Qi, Qi-l) of respective binary numbers which are the ones complement of binary numbers R o ...R N representing each respective output value of the decoder in accordance with the following expression:

    Ai ⊕ Bi ⊕ Qi ⊕ (Ai-l-Bi-l + Qi-l. (Ai-l + Bi-l)).


    The predetermined condition is then satisfied when the above expression has a logic value of ONE.
    A plurality of AND gates are associated respectively with the outputs of the decoder and are each arranged to receive the outputs of the n+l logic circuits for each output value of the decoder.
    The decoder performs addition and decoding in one step.

    Abstract translation: 解码器具有多个输出（Ro-RN），每个输出与特定输出值相关联，并且被布置为将两个二进制数（A，B）相加，并且根据所述和的结果来选择所述输出之一。 解码器包括多个逻辑电路，每个逻辑电路被布置为接收要相加的第一和第二二进制数的相应位，所述逻辑电路被布置为根据所述位的逻辑状态为每个输出值提供相应的结果 以及表示解码器的特定输出值的二进制数的各个比特的逻辑状态; 以及逻辑装置，用于通过与解码器的输出值相关联的逻辑电路的所有结果来确定何时满足预定条件，由此选择该输出值。 在优选实施例中，为了将两个n位数相加在一起，存在n + 1个逻辑电路（L），每个逻辑电路（L）被布置成接收第一和第i位的第i和第i位（Ai，Ai-1，Bi，Bi-1） 和第二n位数，并且每个被配置为根据所述位的逻辑状态以及作为其的各个二进制数的第i和第i-1位（Qi，Qi-1）的逻辑状态提供输出 Ai（+）Bi（+）Qi（+）（Ai-1-Bi-1 + Qi-1。（） Ai-1 + Bi-1））。 当上述表达式的逻辑值为1时，则满足预定条件。 多个与门分别与解码器的输出相关联，并且各自被布置为接收解码器的每个输出值的n + 1个逻辑电路的输出。 解码器在一个步骤中执行加法和解码。

    Memory accessing
    3.
    发明公开
    Memory accessing 失效
    Speicheradressierung。

    公开(公告)号：EP0389142A2

    公开(公告)日：1990-09-26

    申请号：EP90302343.0

    申请日：1990-03-06

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Wise, Adrian Philip ,  Forsyth, Richard Matthew

    IPC: G11C7/00 ,  G11C11/41 ,  G11C8/00

    CPC classification number: G11C11/419 ,  G11C7/10 ,  G11C7/1018

    Abstract: A line delay device comprises a memory having RAM cells in two blocks (14,15), each cell being connected to a pair of bit lines. Memory locations in one block (14) are addressed sequentially and subject to a data transfer while an equate operation is effected on the bit lines of the other block (15). The operations are switched alternately between the two blocks (14,15). In each accessing cycle a plurality of locations are addressed in selected rows of each block (14,15) and the switching between each block is effected without addressing all locations in each row addressed so that the accessing cycle ends in a different block (15) from the starting block (14) and each row used has a plurality of addressed locations.

    Abstract translation: 行延迟装置包括具有两个块（14,15）中的RAM单元的存储器，每个单元连接到一对位线。 一个块（14）中的存储器位置被顺序地寻址并经受数据传输，同时在另一个块（15）的位线上进行相等的操作。 操作在两个块（14,15）之间交替切换。 在每个访问周期中，在每个块（14,15）的选定行中寻址多个位置，并且实现每个块之间的切换而不寻址每行寻址的所有位置，使得访问周期以不同的块（15）结束， 来自起始块（14）并且使用的每一行具有多个寻址位置。

    Multiple instruction issue
    4.
    发明公开
    Multiple instruction issue 失效
    多指令问题

    公开(公告)号：EP0492968A3

    公开(公告)日：1994-11-30

    申请号：EP91311769.3

    申请日：1991-12-18

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Azmoodeh, Saeid ,  Boffey, Peter Malcolm Keith ,  Forsyth, Richard Matthew ,  Parsons, Brian Jeremy

    IPC: G06F9/38

    CPC classification number: G06F9/3822 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885

    Abstract: Computer appratus includes an instruction execution unit (13) having a plurality of functional units (14,16) each arranged to execute at least part of an instruction and instruction issuing circuitry (10,12) for issuing simultaneously a group of separate compatible instructions to the execution unit (13) the circuitry (12) having means for classifying each instruction in dependence on the or each functional unit required for execution of that instruction and means for testing the classification of successive instructions and selecting a group which according to their classification are compatible for simultaneous issue to the execution unit (13) without conflicting demands on any function unit (14,16) in the execution unit.

    Memory accessing
    5.
    发明公开
    Memory accessing 失效
    存储器访问

    公开(公告)号：EP0389142A3

    公开(公告)日：1992-07-15

    申请号：EP90302343.0

    申请日：1990-03-06

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Wise, Adrian Philip ,  Forsyth, Richard Matthew

    IPC: G11C7/00 ,  G11C11/41 ,  G11C8/00

    CPC classification number: G11C11/419 ,  G11C7/10 ,  G11C7/1018

    Abstract: A line delay device comprises a memory having RAM cells in two blocks (14,15), each cell being connected to a pair of bit lines. Memory locations in one block (14) are addressed sequentially and subject to a data transfer while an equate operation is effected on the bit lines of the other block (15). The operations are switched alternately between the two blocks (14,15). In each accessing cycle a plurality of locations are addressed in selected rows of each block (14,15) and the switching between each block is effected without addressing all locations in each row addressed so that the accessing cycle ends in a different block (15) from the starting block (14) and each row used has a plurality of addressed locations.

    Multiple instruction issue
    6.
    发明公开
    Multiple instruction issue 失效
    Mehrfachbefehlausgabe。

    公开(公告)号：EP0492968A2

    公开(公告)日：1992-07-01

    申请号：EP91311769.3

    申请日：1991-12-18

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Azmoodeh, Saeid ,  Boffey, Peter Malcolm Keith ,  Forsyth, Richard Matthew ,  Parsons, Brian Jeremy

    IPC: G06F9/38

    CPC classification number: G06F9/3822 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885

    Abstract: Computer appratus includes an instruction execution unit (13) having a plurality of functional units (14,16) each arranged to execute at least part of an instruction and instruction issuing circuitry (10,12) for issuing simultaneously a group of separate compatible instructions to the execution unit (13) the circuitry (12) having means for classifying each instruction in dependence on the or each functional unit required for execution of that instruction and means for testing the classification of successive instructions and selecting a group which according to their classification are compatible for simultaneous issue to the execution unit (13) without conflicting demands on any function unit (14,16) in the execution unit.

    Abstract translation: 计算机设备包括具有多个功能单元（14,16）的指令执行单元（13），每个功能单元（14,16）被布置为执行指令和指令发布电路（10,12）的至少一部分，用于同时发出一组单独的兼容指令 执行单元（13）具有用于根据执行该指令所需的或每个功能单元对每个指令进行分类的装置，以及用于测试连续指令的分类的装置以及根据其分类选择的组 兼容于执行单元（13）的同时发布，而对执行单元中的任何功能单元（14,16）没有冲突的要求。

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