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    TOUCH PANEL
    2.
    发明专利
    TOUCH PANEL 未知

    公开(公告)号：SG11201502396SA

    公开(公告)日：2015-05-28

    申请号：SG11201502396S

    申请日：2013-05-17

    Applicant: SHARP KK

    Inventor： KIDA KAZUTOSHI ,  HAYASHI SHOGO

    IPC: G06F3/041

    Abstract: An arrangement is provided that uses the differential approach to effectively remove noise contained in a signal in a line even in a touch panel that includes some lines that are separated from each other at a larger distance. The touch panel (2) includes: a touch panel substrate (22), a plurality of Y-direction electrodes (23) provided on the touch panel substrate (22); a plurality of lines (24, 34) electrically connected with the Y-direction electrodes (23); and a floating electrode (61) located within a predetermined distance from at least one of the lines (24, 34) and another line adjacent the at least one line such that noise produced in the at least one line can be propagated to reach the other line.

    DISTRIBUTED COMPUTING SYSTEM
    5.
    发明专利
    DISTRIBUTED COMPUTING SYSTEM 失效

    公开(公告)号：JPH0764892A

    公开(公告)日：1995-03-10

    申请号：JP21074993

    申请日：1993-08-25

    Applicant: SHARP KK

    Inventor： HAYASHI SHOGO

    IPC: G06F13/00 ,  G06F15/16 ,  G06F15/177

    Abstract: PURPOSE:To increase or decrease a CPU server without setting an individual server, and to always select the optimal CPU server at the time of activating a request by separately providing a request server, and unitaryly managing CPU server information with the request server. CONSTITUTION:The request server 200 is separately provided, and the CPU server information is unitaryly managed. The request server 200 communicates with CPU servers 300, 310, 320, and 330, an evaluates the latest up-to-date CPU server processing information updated at the time of starting and stopping the CPU servers 310, 320, and 330 in the sequence of program executing requests received from clients 100, 110, 120, and 130, and makes a request to the proper CPU server to be executed. the request server 200 operates the queuing of the requests received from the clients 100, 110, 120, and 130. Therefore, at the time of increasing the CPU server, the capability information of the CPU server or the like is inputted to the request server 200.

    MULTIPROGRAM EXECUTION MANAGMENT METHOD
    7.
    发明专利
    MULTIPROGRAM EXECUTION MANAGMENT METHOD 失效

    公开(公告)号：JPH06202884A

    公开(公告)日：1994-07-22

    申请号：JP90593

    申请日：1993-01-07

    Applicant: SHARP KK

    Inventor： HAYASHI SHOGO

    IPC: G06F9/46

    Abstract: PURPOSE:To shorten the real execution time for each program by giving the CPU occupancy right to each program in the time division system in a general computer system without the specific limit of the feature and number to the program to be executed. CONSTITUTION:In executing plural programs at the same time, the scheduling priority degree is computed by the consumption amount of CPU being the time when each program being executed occupies the CPU, required CPU time corresponding to the CPU occupancy time required for the execution, the average running number of the program which occupies the CPU within the constant time and the load factor value set by a user. According to the scheduling priority order, each running program is stored and executed. The maximum value and the average time of the CPU occupancy time required for the execution of each program are held as the execution data. In executing a new program, the execution data are sent to a scheduling program 2 as the request CPU time.

    METHOD AND APPARATUS FOR TREATMENT OF ROM PATTERN
    8.
    发明专利
    METHOD AND APPARATUS FOR TREATMENT OF ROM PATTERN 失效

    公开(公告)号：JPH04330714A

    公开(公告)日：1992-11-18

    申请号：JP8184691

    申请日：1991-03-19

    Applicant: SHARP KK

    Inventor： HAYASHI SHOGO ,  MIYANO HIROSHI

    IPC: G03F1/00 ,  G03F1/68 ,  H01L21/027 ,  H01L21/66 ,  H01L21/8246 ,  H01L27/112

    Abstract: PURPOSE:To shorten the time required for a data read operation or the like by a method wherein, when a graphic pattern is converted into an lntermediate data which can be processed by a mask formation device and the intermediate data is composed as a final output data, the intermediate data is converted in parallel. CONSTITUTION:A multiprocessor part 300 is provided with a plurality of expansion and conversion mechanisms; the individual expansion and conversion mechanisms 310 are actuated in parallel independently of each other. The expansion and conversion mechanisms 310 are provided with the following: a function to form a graphic pattern F from coordinates B; and a function to convert the graphic pattern F into intermediate data C which can be processed by an electron beam device. A memory part 200 forms the graphic pattern F based on the coordinates B and preferentially outputs the coordinates B to the expansion and conversion mechanisms 310 which have finished the conversion into the intermediate data C. Consequently, the time required to input all the coordinates B stored in the memory part 200 to the multiprocessor part 300 is shortened as compared with that in conventional cases.

    WIRING FOR INTEGRATED CIRCUIT
    9.
    发明专利
    WIRING FOR INTEGRATED CIRCUIT 失效

    公开(公告)号：JPS61166142A

    公开(公告)日：1986-07-26

    申请号：JP785985

    申请日：1985-01-18

    Applicant: SHARP KK

    Inventor： HAYASHI SHOGO

    IPC: H01L21/3205 ,  H01L21/82 ,  H01L23/52

    Abstract: PURPOSE:To enable to rapidly decide a wiring ranging from its one end to its other end without spending a wasteful labor hour by a method wherein a clearance with the prescribed interval to the segments for the wiring route decided at first is set on the inner side of the wiring region and a new wiring region boundary line is formed. CONSTITUTION:Before the first wiring route is decided, a boundary line 2 with a clearance to the frame of a wiring region 1 is formed on the periphery of the inner side of the wiring region 1. After that, after segments, which are used as the wiring ranging from a starting end Si to a terminal Ti, are decided according to the prescribed procedures, segments bi1, Bi2...bil parallel to the segments decided are formed in the residual wiring region in such a way as to have a clearance width to the segments decided for setting a clearance for the following wiring to be formed adjacent to the wiring decided at first. A boundary line 3 to show the residual wiring region is anew formed from both of the segments bi1...bil formed according to these procedures and the boundary line 2 formed at first. This boundary line 3 gives a direction needed for deciding the following wiring route.

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