公开(公告)号：US20160267946A1

公开(公告)日：2016-09-15

申请号：US15032935

申请日：2014-10-27

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Sang Wook Ahn ,  Huy Chan Jung ,  Yong Woon Lee ,  Heui-Gyun Ahn ,  Do Young Lee

IPC: G11C5/02 ,  G11C8/06 ,  G11C8/10 ,  H01L25/065 ,  G11C5/06 ,  H01L23/48

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/06 ,  G11C8/10 ,  H01L23/48 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a stack memory device and a method for operating same. The stack memory device, according to the present invention, is provided with: a first memory chip in which first type memory cells are repeatedly arranged in row direction and column direction, and which comprises one or more cell arrays, in which a dump line is connected to the each first type memory cell; and a second memory chip in which second type memory cells are repeatedly arranged in row direction and column direction, and which comprises one or more cell arrays, in which a dump line is connected to the each second type memory cell, wherein first pads are connected to the dump lines of the first type memory cells and second pads are connected to the dump lines of the second type memory cells, the first pads and the second pads having one-to-one correspondence.

Abstract translation: 本发明提供了一种堆栈存储装置及其操作方法。 根据本发明的堆叠存储器件提供有：第一存储器芯片，其中第一类型存储器单元在行方向和列方向上重复布置，并且包括一个或多个单元阵列，其中转储线是 连接到每个第一类型存储单元; 以及第二存储器芯片，其中第二类型存储器单元在行方向和列方向上重复排列，并且包括一个或多个单元阵列，其中转储线连接到每个第二类型存储单元，其中第一焊盘被连接 到第一类型存储单元的转储线和第二焊盘连接到第二类型存储单元的转储线，第一焊盘和第二焊盘具有一一对应关系。

公开(公告)号：US08993411B2

公开(公告)日：2015-03-31

申请号：US13775178

申请日：2013-02-23

Applicant: Siliconfile Technologies Inc.

Inventor： Heui-Gyun Ahn ,  Se-Jung Oh ,  In-Gyun Jeon ,  Jun-Ho Won

IPC: H01L21/46 ,  H01L23/00 ,  H01L21/683 ,  H01L23/48 ,  H01L27/146

CPC classification number: H01L24/03 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/05 ,  H01L27/1462 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2221/68372 ,  H01L2224/05093 ,  H01L2924/01046 ,  H01L2924/01078

Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, filling one or more metals in the vias and the defined space for the pad, and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.

Abstract translation: 公开了一种用于在具有三维堆叠结构的晶片中形成焊盘的方法。 该方法包括将包括Si衬底和处理晶片的器件晶片接合，使Si衬底的背面变薄，在Si衬底的减薄的背侧上沉积抗反射层，在其上沉积背面电介质层 防反射层，在背面电介质层中形成用于焊盘的空间，并且形成穿过形成在Si衬底上的超级触点的背面电介质层和抗反射层和接触背面的通孔，填充 通孔中的一种或多种金属和用于垫的限定空间，以及通过CMP（化学机械抛光）工艺通过平坦化除去填充在垫的空间中的剩余量的金属。

公开(公告)号：US09406652B2

公开(公告)日：2016-08-02

申请号：US14891635

申请日：2014-05-12

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Sang Wook Ahn ,  Huy Chan Jung ,  Yong Woon Lee ,  Do Young Lee ,  Heui-Gyun Ahn

IPC: G11C5/06 ,  H01L25/065 ,  H01L23/528 ,  G11C7/06 ,  G11C7/10

CPC classification number: H01L25/0657 ,  G11C5/063 ,  G11C7/06 ,  G11C7/10 ,  G11C2207/005 ,  H01L23/49816 ,  H01L23/528 ,  H01L25/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A semiconductor memory is formed by stacking a plurality of substrates and memory cells on each substrate are connected by data dump lines. A switch may intervene between the memory cell and the data dump line. When data of each substrate is dumped by the data dump line, a problem of decrease in a speed and an increase in power consumption due to a parasitic component can be minimized. Further, a core circuit including the memory cell may be disposed on one substrate and a peripheral circuit unit may be disposed on the remaining substrates.

Abstract translation: 通过堆叠多个基板形成半导体存储器，并且通过数据转储线连接每个基板上的存储单元。 交换机可以介入存储器单元和数据转储线之间。 当每个基板的数据被数据转储线转储时，由于寄生成分引起的速度下降和功耗增加的问题可以被最小化。 此外，包括存储单元的核心电路可以设置在一个基板上，并且外围电路单元可以设置在剩余的基板上。