公开(公告)号：US09553120B2

公开(公告)日：2017-01-24

申请号：US14529783

申请日：2014-10-31

Applicant: SiliconFile Technologies Inc.

Inventor： Jae Young Park ,  Young Ha Lee ,  Jun Ho Won ,  Do Young Lee

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/1469

Abstract: A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.

Abstract translation: 这种技术能够简化工艺并且在使用背面照明光电二极管接合两个晶片以制造图像传感器时确保不对准裕度。 当通过3D CIS（CMOS图像传感器）制造工艺制造图像传感器时，使用一个晶片的通孔和另一个晶片的焊盘来电连接两个晶片，即第一晶片和第二晶片。 此外，当通过3D CIS制造工艺制造图像传感器时，两个晶片使用两个晶片的通孔电连接。

公开(公告)号：US09478464B2

公开(公告)日：2016-10-25

申请号：US14888674

申请日：2014-04-30

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Heui Gyun Ahn ,  Sang Wook Ahn ,  Yong Woon Lee ,  Huy Chan Jung ,  Do Young Lee

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/683

CPC classification number: H01L21/76898 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/7684 ,  H01L2221/68327 ,  H01L2221/68359

Abstract: A method for manufacturing a through-hole silicon via (TSV) employs the conventional trench insulation process to readily manufacture a through-hole silicon via (TSV) with achievement of an effective electrical insulation between the through-hole silicon via (TSV) and the silicon.

Abstract translation: 用于制造通孔硅通孔（TSV）的方法采用传统的沟槽绝缘工艺来容易地制造通孔硅通孔（TSV），从而实现通孔硅通孔（TSV）和通孔硅通孔（TSV）之间的有效电绝缘 硅。

公开(公告)号：US09337232B2

公开(公告)日：2016-05-10

申请号：US14359264

申请日：2012-11-08

Applicant: SiliconFile Technologies Inc.

Inventor： Do Young Lee

IPC: H01L27/146

CPC classification number: H01L27/14647 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14641

Abstract: The present invention relates to a substrate stacked image sensor having a dual detection function, in which when first to fourth photodiodes are formed in a first substrate, a fifth photodiode is formed in a second substrate, and the substrates are stacked and combined with each other, the first to fourth photodiodes and the fifth photodiode are combined with each other to obtain a complete photodiode as an element of one pixel, and signals individually detected in each photodiode are selectively read or added to be read according to necessity. To this end, the first to fourth photodiodes are formed in the first substrate, the fifth photodiode is formed in the second substrate, the first to fourth photodiodes and the fifth photodiode make electrical contact with each other, and pixel array sizes of the first substrate and the second substrate are allowed to be different from each other, so that sensor resolution of the first substrate and sensor resolution of the second substrate are different from each other.

Abstract translation: 本发明涉及具有双重检测功能的基板层叠图像传感器，其中当在第一基板中形成第一至第四光电二极管时，在第二基板中形成第五光电二极管，并且将基板彼此堆叠并组合 ，第一至第四光电二极管和第五光电二极管彼此组合以获得作为一个像素的元件的完整光电二极管，并且根据需要选择性地读取或添加在每个光电二极管中单独检测的信号以进行读取。 为此，第一至第四光电二极管形成在第一衬底中，第五光电二极管形成在第二衬底中，第一至第四光电二极管和第五光电二极管彼此电接触，第一衬底的像素阵列尺寸 并且第二基板被允许彼此不同，使得第一基板的传感器分辨率和第二基板的传感器分辨率彼此不同。

公开(公告)号：US20140327061A1

公开(公告)日：2014-11-06

申请号：US14359264

申请日：2012-11-08

Applicant: SiliconFile Technologies Inc.

Inventor： Do Young Lee

IPC: H01L27/146

CPC classification number: H01L27/14647 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14641

Abstract: The present invention relates to a substrate stacked image sensor having a dual detection function, in which when first to fourth photodiodes are formed in a first substrate, a fifth photodiode is formed in a second substrate, and the substrates are stacked and combined with each other, the first to fourth photodiodes and the fifth photodiode are combined with each other to obtain a complete photodiode as an element of one pixel, and signals individually detected in each photodiode are selectively read or added to be read according to necessity. To this end, the first to fourth photodiodes are formed in the first substrate, the fifth photodiode is formed in the second substrate, the first to fourth photodiodes and the fifth photodiode make electrical contact with each other, and pixel array sizes of the first substrate and the second substrate are allowed to be different from each other, so that sensor resolution of the first substrate and sensor resolution of the second substrate are different from each other.

Abstract translation: 本发明涉及具有双重检测功能的基板层叠图像传感器，其中当在第一基板中形成第一至第四光电二极管时，在第二基板中形成第五光电二极管，并且将基板彼此堆叠并组合 ，第一至第四光电二极管和第五光电二极管彼此组合以获得作为一个像素的元件的完整光电二极管，并且根据需要选择性地读取或添加在每个光电二极管中单独检测的信号以进行读取。 为此，第一至第四光电二极管形成在第一衬底中，第五光电二极管形成在第二衬底中，第一至第四光电二极管和第五光电二极管彼此电接触，第一衬底的像素阵列尺寸 并且第二基板被允许彼此不同，使得第一基板的传感器分辨率和第二基板的传感器分辨率彼此不同。

公开(公告)号：US09406652B2

公开(公告)日：2016-08-02

申请号：US14891635

申请日：2014-05-12

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Sang Wook Ahn ,  Huy Chan Jung ,  Yong Woon Lee ,  Do Young Lee ,  Heui-Gyun Ahn

IPC: G11C5/06 ,  H01L25/065 ,  H01L23/528 ,  G11C7/06 ,  G11C7/10

CPC classification number: H01L25/0657 ,  G11C5/063 ,  G11C7/06 ,  G11C7/10 ,  G11C2207/005 ,  H01L23/49816 ,  H01L23/528 ,  H01L25/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A semiconductor memory is formed by stacking a plurality of substrates and memory cells on each substrate are connected by data dump lines. A switch may intervene between the memory cell and the data dump line. When data of each substrate is dumped by the data dump line, a problem of decrease in a speed and an increase in power consumption due to a parasitic component can be minimized. Further, a core circuit including the memory cell may be disposed on one substrate and a peripheral circuit unit may be disposed on the remaining substrates.

Abstract translation: 通过堆叠多个基板形成半导体存储器，并且通过数据转储线连接每个基板上的存储单元。 交换机可以介入存储器单元和数据转储线之间。 当每个基板的数据被数据转储线转储时，由于寄生成分引起的速度下降和功耗增加的问题可以被最小化。 此外，包括存储单元的核心电路可以设置在一个基板上，并且外围电路单元可以设置在剩余的基板上。

公开(公告)号：US09484377B2

公开(公告)日：2016-11-01

申请号：US14649710

申请日：2013-11-15

Applicant: SiliconFile Technologies Inc.

Inventor： Jun Ho Won ,  Won Ho Lee ,  Do Young Lee

IPC: H01L27/146 ,  H04N9/04

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14645 ,  H01L27/14649 ,  H01L27/14685 ,  H01L27/14689 ,  H04N9/045

Abstract: The present invention relates to a CMOS image sensor including an infrared pixel with enhanced spectral characteristics in which a stepped portion is formed between color filters of RGB pixels and a filter of an infrared pixel, and a manufacturing method thereof. A stepped portion is formed between color filters and an infrared filter according to respective pixels and the thicknesses of the filters are arbitrarily adjusted regardless of the characteristics of material in the formation of the color filters and the infrared filter, so that crosstalk characteristics are improved.

Abstract translation: 本发明涉及一种CMOS图像传感器及其制造方法，该CMOS图像传感器包括具有增强的光谱特性的红外像素及其制造方法，其中在RGB像素的滤色器和红外像素的滤色器之间形成台阶部分。 根据各个像素，在滤色器和红外滤光器之间形成阶梯部分，并且无论滤色器和红外滤光器的形成中的材料的特性如何，都可任意调节滤光片的厚度，从而提高串扰特性。

公开(公告)号：US20160267946A1

公开(公告)日：2016-09-15

申请号：US15032935

申请日：2014-10-27

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Sang Wook Ahn ,  Huy Chan Jung ,  Yong Woon Lee ,  Heui-Gyun Ahn ,  Do Young Lee

IPC: G11C5/02 ,  G11C8/06 ,  G11C8/10 ,  H01L25/065 ,  G11C5/06 ,  H01L23/48

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/06 ,  G11C8/10 ,  H01L23/48 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a stack memory device and a method for operating same. The stack memory device, according to the present invention, is provided with: a first memory chip in which first type memory cells are repeatedly arranged in row direction and column direction, and which comprises one or more cell arrays, in which a dump line is connected to the each first type memory cell; and a second memory chip in which second type memory cells are repeatedly arranged in row direction and column direction, and which comprises one or more cell arrays, in which a dump line is connected to the each second type memory cell, wherein first pads are connected to the dump lines of the first type memory cells and second pads are connected to the dump lines of the second type memory cells, the first pads and the second pads having one-to-one correspondence.

Abstract translation: 本发明提供了一种堆栈存储装置及其操作方法。 根据本发明的堆叠存储器件提供有：第一存储器芯片，其中第一类型存储器单元在行方向和列方向上重复布置，并且包括一个或多个单元阵列，其中转储线是 连接到每个第一类型存储单元; 以及第二存储器芯片，其中第二类型存储器单元在行方向和列方向上重复排列，并且包括一个或多个单元阵列，其中转储线连接到每个第二类型存储单元，其中第一焊盘被连接 到第一类型存储单元的转储线和第二焊盘连接到第二类型存储单元的转储线，第一焊盘和第二焊盘具有一一对应关系。

公开(公告)号：US20150115330A1

公开(公告)日：2015-04-30

申请号：US14529783

申请日：2014-10-31

Applicant: SiliconFile Technologies Inc.

Inventor： Jae Young Park ,  Young Ha Lee ,  Jun Ho Won ,  Do Young Lee

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/1469

Abstract: A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.

Abstract translation: 这种技术能够简化工艺并且在使用背面照明光电二极管接合两个晶片以制造图像传感器时确保不对准裕度。 当通过3D CIS（CMOS图像传感器）制造工艺制造图像传感器时，使用一个晶片的通孔和另一个晶片的焊盘来电连接两个晶片，即第一晶片和第二晶片。 此外，当通过3D CIS制造工艺制造图像传感器时，两个晶片使用两个晶片的通孔电连接。