Abstract:
An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.
Abstract:
A radio frequency (RF) filter circuit for rejecting one or more spurious components of an input signal has a first resonator circuit including a first capacitor and a first coupled inductor pair of a first inductor and a second inductor, and a second resonator circuit with a second capacitor and a second coupled inductor pair of a third inductor and a fourth inductor. First and second resonator coupling capacitors are connected to the first resonator circuit and the second resonator circuit. A first port and a second port are connected to the first resonator circuit and the second resonator, with the filtered signal of the input signal passed through both the first resonator circuit and the second resonator circuit being output.
Abstract:
An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain.