公开(公告)号：WO2004095515B1

公开(公告)日：2005-03-17

申请号：PCT/US2004011872

申请日：2004-04-16

Applicant: FREESCALE SEMICONDUCTOR INC ,  GRYNKEWICH GREGORY W ,  BUTCHER BRIAN R ,  DURLAM MARK A ,  KYLER KELLY ,  SNYDER CHARLES A ,  SMITH KENNETH H ,  TRACY CLARENCE J

Inventor： GRYNKEWICH GREGORY W ,  BUTCHER BRIAN R ,  DURLAM MARK A ,  KYLER KELLY ,  SNYDER CHARLES A ,  SMITH KENNETH H ,  TRACY CLARENCE J ,  WILLIAMS RICHARD

IPC: G11C11/15 ,  H01L21/8246 ,  H01L43/12 ,  G11C8/02 ,  G11C11/00 ,  H01L43/00

CPC classification number: H01L27/222 ,  B82Y10/00 ,  G11C11/15 ,  H01L43/12

Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer (26) is deposited overlying the memory element layer (18). A first dielectric layer (28) is deposited overlying the first electrically conductive layer (26) and is patterned and etched to form a first masking layer (28). Using the first masking layer (28), the first electrically conductive layer (26) is etched. A second dielectric layer (36) is deposited overlying the first masking layer (28) and the dielectric region. A portion of the second dielectric layer (36) is removed to expose the first masking layer (28). The second dielectric layer (36) and the first masking layer (28) are subjected to an etching chemistry such that the first masking layer (28) is etched at a faster rate than the second dielectric layer (36). The etching exposes the first electrically conductive layer (26).

Abstract translation: 用于接触覆盖磁电元件的导电层的方法包括形成覆盖介电区域的存储元件层。 沉积第一导电层（26），覆盖存储元件层（18）。 沉积覆盖第一导电层（26）的第一介电层（28），并将其图案化并蚀刻以形成第一掩模层（28）。 使用第一掩模层（28），蚀刻第一导电层（26）。 沉积覆盖第一掩模层（28）和介电区域的第二介电层（36）。 第二电介质层（36）的一部分被去除以暴露第一掩模层（28）。 对第二介电层（36）和第一掩模层（28）进行蚀刻化学处理，使得以比第二介电层（36）更快的速率蚀刻第一掩模层（28）。 蚀刻暴露第一导电层（26）。

公开(公告)号：WO2006055179A3

公开(公告)日：2006-08-03

申请号：PCT/US2005038153

申请日：2005-10-25

Applicant: FREESCALE SEMICONDUCTOR INC ,  BUTCHER BRIAN R ,  GRYNKEWICH GREGORY W ,  KYLER KELLY W ,  SMITH KENNETH H ,  WILLIAMS RICHARD G

Inventor： BUTCHER BRIAN R ,  GRYNKEWICH GREGORY W ,  KYLER KELLY W ,  SMITH KENNETH H ,  WILLIAMS RICHARD G

IPC: H01L43/00 ,  H01L21/00

CPC classification number: H01L43/12 ,  H01L27/226

Abstract: Structures for electrical communication with an overlying electrode for a semiconductor element and methods for fabricating such structures are provided. The structure (10) for electrical communication with an overlying electrode comprises a first electrode (50) having a lateral dimension, a semiconductor element (14) overlying the first electrode, and a second electrode (30) overlying the semiconductor element. The second electrode (30) has a lateral dimension that is less than the lateral dimension of the first electrode (50). A conductive hardmask (42) overlies the second electrode and is in electrical communication with the second electrode. The conductive hardmask (42) has a lateral dimension that is substantially equal to the lateral dimension of the first electrode. A conductive contact element (56) is in electrical communication with the conductive hardmask.

Abstract translation: 提供了用于与半导体元件的上覆电极的电连通的结构以及用于制造这种结构的方法。 用于与上覆电极电连通的结构（10）包括具有横向尺寸的第一电极（50），覆盖第一电极的半导体元件（14）和覆盖半导体元件的第二电极（30）。 第二电极（30）具有小于第一电极（50）的横向尺寸的横向尺寸。 导电硬掩模（42）覆盖第二电极并与第二电极电连通。 导电硬掩模（42）具有基本上等于第一电极的横向尺寸的横向尺寸。 导电接触元件（56）与导电硬掩模电连通。

公开(公告)号：US3230993A

公开(公告)日：1966-01-25

申请号：US37952864

申请日：1964-07-01

Applicant: SMITH

Inventor： SMITH KENNETH H ,  ANDREW JOHN T

IPC: B42D3/04

CPC classification number: B42D3/04 ,  B42P2201/00 ,  Y10S428/913

公开(公告)号：US2524937A

公开(公告)日：1950-10-10

申请号：US68757646

申请日：1946-08-01

Applicant: SMITH KENNETH H

Inventor： SMITH KENNETH H

IPC: A01B19/02

CPC classification number: A01B19/02

公开(公告)号：WO2004095515A8

公开(公告)日：2005-11-17

申请号：PCT/US2004011872

申请日：2004-04-16

Applicant: FREESCALE SEMICONDUCTOR INC ,  GRYNKEWICH GREGORY W ,  BUTCHER BRIAN R ,  DURLAM MARK A ,  KYLER KELLY ,  SNYDER CHARLES A ,  SMITH KENNETH H ,  TRACY CLARENCE J

Inventor： GRYNKEWICH GREGORY W ,  BUTCHER BRIAN R ,  DURLAM MARK A ,  KYLER KELLY ,  SNYDER CHARLES A ,  SMITH KENNETH H ,  TRACY CLARENCE J ,  WILLIAMS RICHARD

IPC: G11C11/15 ,  H01L21/8246 ,  H01L43/12 ,  G11C8/02 ,  G11C11/00 ,  H01L43/00

CPC classification number: H01L27/222 ,  B82Y10/00 ,  G11C11/15 ,  H01L43/12

Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer (26) is deposited overlying the memory element layer (18). A first dielectric layer (28) is deposited overlying the first electrically conductive layer (26) and is patterned and etched to form a first masking layer (28). Using the first masking layer (28), the first electrically conductive layer (26) is etched. A second dielectric layer (36) is deposited overlying the first masking layer (28) and the dielectric region. A portion of the second dielectric layer (36) is removed to expose the first masking layer (28). The second dielectric layer (36) and the first masking layer (28) are subjected to an etching chemistry such that the first masking layer (28) is etched at a faster rate than the second dielectric layer (36). The etching exposes the first electrically conductive layer (26).

Abstract translation: 用于使覆盖磁电元件的导电层接触的方法包括形成覆盖在电介质区域上的存储元件层。 沉积在存储元件层（18）上的第一导电层（26）。 沉积覆盖在第一导电层（26）上的第一介电层（28）并被图案化和蚀刻以形成第一掩模层（28）。 使用第一掩模层（28），蚀刻第一导电层（26）。 沉积在第一掩模层（28）和电介质区域上的第二介电层（36）。 去除第二介电层（36）的一部分以露出第一掩模层（28）。 对第二介电层（36）和第一掩模层（28）进行蚀刻化学处理，使得以比第二介电层（36）更快的速率蚀刻第一掩模层（28）。 蚀刻暴露第一导电层（26）。

公开(公告)号：WO2004095515A3

公开(公告)日：2005-01-27

申请号：PCT/US2004011872

申请日：2004-04-16

Applicant: FREESCALE SEMICONDUCTOR INC ,  GRYNKEWICH GREGORY W ,  BUTCHER BRIAN R ,  DURLAM MARK A ,  KYLER KELLY ,  SNYDER CHARLES A ,  SMITH KENNETH H ,  TRACY CLARENCE J

Inventor： GRYNKEWICH GREGORY W ,  BUTCHER BRIAN R ,  DURLAM MARK A ,  KYLER KELLY ,  SNYDER CHARLES A ,  SMITH KENNETH H ,  TRACY CLARENCE J ,  WILLIAMS RICHARD

IPC: G11C11/15 ,  H01L21/8246 ,  H01L43/12 ,  G11C8/02 ,  G11C11/00 ,  H01L43/00

CPC classification number: H01L27/222 ,  B82Y10/00 ,  G11C11/15 ,  H01L43/12

Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer (26) is deposited overlying the memory element layer (18). A first dielectric layer (28) is deposited overlying the first electrically conductive layer (26) and is patterned and etched to form a first masking layer (28). Using the first masking layer (28), the first electrically conductive layer (26) is etched. A second dielectric layer (36) is deposited overlying the first masking layer (28) and the dielectric region. A portion of the second dielectric layer (36) is removed to expose the first masking layer (28). The second dielectric layer (36) and the first masking layer (28) are subjected to an etching chemistry such that the first masking layer (28) is etched at a faster rate than the second dielectric layer (36). The etching exposes the first electrically conductive layer (26).