公开(公告)号：EP2819402A4

公开(公告)日：2016-02-24

申请号：EP12869246

申请日：2012-12-17

Applicant: SONY CORP

Inventor： TAMAYAMA KEN ,  FUJINAWA AKIRA ,  SHIMIZU MASAYUKI ,  IKEDA KIYOSHI

IPC: H04N5/74 ,  G02B27/01 ,  G09G3/20 ,  G09G5/00 ,  G09G5/36 ,  G09G5/38 ,  G09G5/391 ,  H04N5/64

CPC classification number: H04N9/3185 ,  G02B27/017 ,  G02B27/0172 ,  G02B2027/011 ,  G02B2027/014 ,  G09G3/002 ,  G09G5/005 ,  G09G5/391 ,  G09G2340/04 ,  H04N5/145 ,  H04N5/64 ,  H04N9/3129 ,  H04N9/3188 ,  H04N13/0468

Abstract: Provided is a display device including an image display unit configured to display an image with a plurality of pixels arranged on a display surface, an eyepiece optical unit configured to project the display surface of the image display unit in a manner that a predetermined angle of view is obtained, and an image correction unit configured to correct a display image on the display surface at a position of each of representative pixels which are discretely located on the display surface, on the basis of distortion generated due to the eyepiece optical unit.

Abstract translation: 提供了一种显示装置，包括：图像显示单元，被配置为显示具有布置在显示表面上的多个像素的图像;目镜光学单元，被配置为以预定视角投影图像显示单元的显示表面; 以及图像校正单元，被配置为基于由目镜光学单元产生的失真来校正离散地位于显示表面上的每个代表像素的位置处的显示表面上的显示图像。

公开(公告)号：JPH08102140A

公开(公告)日：1996-04-16

申请号：JP23686794

申请日：1994-09-30

Applicant: SONY CORP

Inventor： FUJINAWA AKIRA

IPC: G11B20/10 ,  G11B19/12 ,  G11B20/12 ,  G11B20/18

Abstract: PURPOSE: To automatically discriminate a data structure of even an MD by performing calculation processing on data read out of a memory in accordance with the data structure discriminated as to whether the data is required for error correction processing or not, at the time of accumulating data in the memory. CONSTITUTION: Data from an optical disk is subjected to demodulation and error correction by a decoding IC in a signal processing circuit 6, and the data is sent to a header extracting circuit 61 and a DMA control circuit 64. The data is once stored in the memory 11 by the circuit 64, and a result of discriminating a data structure by a data structure discriminating circuit 62 from header information inputted and extracted by the circuit 61 is sent to a data calculating circuit 63. At this time, the data accumulated in the memory 11 is sent via the circuit 64 to the circuit 63, and the accumulated data is data-calculated by the circuit 63 in accordance with a discriminating result of the circuit 62. The data obtained by this calculation is again stored in the memory 11, and is outputted from an output terminal 56 by the circuit 64 and a SCSI-IC 24. By this method, even when the MD is used, its data structure can automatically be discriminated, and a calculation corresponding to each data structure can also be carried out.

公开(公告)号：JP2006294098A

公开(公告)日：2006-10-26

申请号：JP2005111008

申请日：2005-04-07

Applicant: Sony Corp ,  ソニー株式会社

Inventor： OMORI TAKASHI ,  FUJINAWA AKIRA

IPC: G11B20/14

Abstract: PROBLEM TO BE SOLVED: To provide a signal processing device and a reproduction device, ensuring stable reproduction even if a disk-like recording medium has an increased recording density. SOLUTION: A gradient of a reproduction signal at a polarity changing point is detected, and when it is a predetermined gradient or less, control is performed such that a detected phase error is canceled. When signal amplitude is reduced by increase in recording density and therefore a signal is subjected to intersymbol interference, a polarity changing point of a reproduction signal at the relevant portion is significantly shifted from a polarity changing point to be originally obtained, thereby a phase error increases and consequently a reference clock may be hard to be normally generated. Since a gradient of the reproduction signal is reduced in such a portion where the signal amplitude of the reproduction signal is reduced and a signal is subjected to intersymbol interference, when the phase error, which is detected in the portion where the gradient of the reproduction signal is a predetermined gradient or less, is canceled as above, adverse influence of a large phase error detected in the portion on reference clock generation operation is eliminated, leading to stable reproduction operation. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了提供信号处理装置和再现装置，即使盘状记录介质具有增加的记录密度，确保稳定再现。 解决方案：检测极性变化点的再现信号的梯度，并且当其为预定斜率或更小时，执行控制以使得检测到的相位误差被消除。 当通过增加记录密度降低信号幅度，因此信号遭受码间干扰时，相关部分的再现信号的极性变化点从原来获得的极性变化点显着偏移，从而相位误差增大 因此参考时钟可能难以正常地产生。 由于在再现信号的信号幅度减小并且信号遭受码间干扰的部分中再现信号的梯度减小，所以当在再现信号的梯度部分中检测到的相位误差 是预定的梯度或更小，如上所述被消除，消除了在该部分中检测到的大的相位误差对参考时钟产生操作的不利影响，导致稳定的再现操作。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JPH06223476A

公开(公告)日：1994-08-12

申请号：JP1179293

申请日：1993-01-27

Applicant: SONY CORP

Inventor： FUJINAWA AKIRA

IPC: G11B17/04 ,  G11B17/043

Abstract: PURPOSE:To prevent various failures caused by recognizing a disk being loaded by a floppy disk controller despite that the disk is ejected. CONSTITUTION:A disk driving device is provided with an FDDCIC 4 which outputs an ejecting motor ON/OFF signal, an ejecting motor 5 which performs an ejecting operation by this signal, a detecting sensor 1 which detects ejection, and an AND circuit 6 which generates a disk in/out detecting signal which indicates loading/unloading of a disk based on these signals. Also, the disk in/out detecting signal obtained by an OR operation with the detecting signal from the detecting sensor and the ejecting motor ON/OFF signal from the FDDCIC is supplied to the FDDCIC 4, thereby, the state of ejecting a disk is unequivocally held independently of timing of ON/OFF operation of the detecting sensor, during ejecting operation of the disk.

公开(公告)号：JPH07271515A

公开(公告)日：1995-10-20

申请号：JP8759694

申请日：1994-03-31

Applicant: SONY CORP

Inventor： FUJINAWA AKIRA

IPC: G06F3/06 ,  G11B7/00 ,  G11B7/005 ,  G11B20/10

Abstract: PURPOSE:To transfer the data of plural bytes stored in a memory to its another area in a simple constitution. CONSTITUTION:When the transfer of information data is started, a control means 4 sets the start address of the storage position of the information data D1 stored in a memory means 12 by a memory control means 13 to a 1st counter. Meanwhile the start address of the transfer destination of the data D1 is set to a 2nd counter together with the byte number of information set in a 3rd counter respectively. Thus the data D1 including plural continuous data on the addresses stored in the means 12 are continuously transferred by control of the means 12 controlled by the means 13 after the transfer of the data D1 is started.

公开(公告)号：JPH01220274A

公开(公告)日：1989-09-01

申请号：JP4659288

申请日：1988-02-29

Applicant: SONY CORP

Inventor： MUTO TAKAYASU ,  FUJINAWA AKIRA ,  YAEGASHI AKIRA ,  NAKANO KATSUHIRO ,  TADA HARUTAKA ,  IKEDA KATSUMI

IPC: G11B21/10

Abstract: PURPOSE:To perform tracking control with high accuracy by performing the tracking control of a magnetic head on a recording track formed on each disk surface corresponding to the correction quantity of reference tracking. CONSTITUTION:Magnetic head position detecting means 6 and (15-19) which output the position detection signal SP of the magnetic heads (4A-4D), and a magnetic disk 3 on whose disk surfaces (3A-3D) servo tracks are formed are provided. Reference tracking correction quantity detecting means 4A-4D, 35, 40, 41, 43, 44, 48, 49, 50, and 51 to perform the positioning of the magnetic heads (4A-4D) on the servo tracks based on the position detection signal SP and to detect the correction quantity of the reference tracking at every disk surfaces (3A-3D) are provided. The tracking control of the magnetic heads (4A-4D) are performed on the recording tracks formed on the disk surfaces (3A-3D) corresponding to the correction quantity of the reference tracking. In such a way, it is possible to prevent a tracking error from being generated, and to perform the tracking control with high accuracy.

公开(公告)号：JP2013192193A

公开(公告)日：2013-09-26

申请号：JP2012058937

申请日：2012-03-15

Applicant: Sony Corp ,  ソニー株式会社

Inventor： HIROTA YOICHI ,  IKEDA KIYOSHI ,  FUJINAWA AKIRA

IPC: H04N9/69 ,  H04N5/64

CPC classification number: G09G5/02 ,  G02B27/017 ,  G02B2027/011 ,  G02B2027/014 ,  G09G5/005 ,  G09G5/006 ,  G09G2320/0276 ,  G09G2320/028 ,  G09G2370/12 ,  H04N9/69 ,  H04N21/4104 ,  H04N21/4402

Abstract: PROBLEM TO BE SOLVED: To suitably correct image distortion due to distortion of a lens by signal processing while suppressing a side effect due to signal processing independent for each color component.SOLUTION: In a distortion correction block for each of RGB colors, an input image signal is subjected to degamma processing to be temporarily converted into a linear image, is then subjected to distortion correction, is thereafter subjected to gamma processing again, and is output. When display is performed by combining a display panel and a lens, image quality degradation due to correction can be reduced. Especially, occurrence of color unevenness and degradation in fineness can be prevented, thereby enabling display of an image of higher image quality.

Abstract translation: 要解决的问题：通过信号处理来适当地校正由于信号处理造成的失真的图像失真，同时抑制由于对于每个颜色分量独立的信号处理的副作用。解决方案：在用于每种RGB颜色的失真校正块中，输入图像 将信号进行脱色处理以暂时转换为线性图像，然后进行失真校正，然后再次进行伽马处理，并输出。 当通过组合显示面板和透镜进行显示时，可以降低由于校正引起的图像质量劣化。 特别地，可以防止颜色不均匀的发生和细度的劣化，从而能够显示更高图像质量的图像。

公开(公告)号：JPH07271516A

公开(公告)日：1995-10-20

申请号：JP8759794

申请日：1994-03-31

Applicant: SONY CORP

Inventor： FUJINAWA AKIRA

IPC: G06F3/06 ,  G11B7/00 ,  G11B7/005 ,  G11B20/10

Abstract: PURPOSE:To continuously transfer the data of plural bytes of discontinuous addresses which are stored in a memory in a simple constitution. CONSTITUTION:The bits of a register 24 are increased and the start address of the storage position of the information data D1 stored in a memory means 12 is set in a 1st counter 20. Meanwhile the end address of the data D1 is set in a 1st register 21. Then the transfer of the data D1 is started by a control means 4, and the start address of the storage position of the 2nd information data D4 which are continuously transferred is substituted for the counter 20 from a 2nd register 22 during the transfer of the data D1. Then the end address of the data D4 is substituted for the register 21 from a 3rd register 23.