公开(公告)号：DE10144700A1

公开(公告)日：2002-04-18

申请号：DE10144700

申请日：2001-09-11

Applicant: SONY CORP

Inventor： KOBAYASHI TOSHIO ,  MORIYA HIROYUKI ,  FUJIWARA ICHIRO

IPC: B82B1/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A non-volatile semiconductor memory has a channel forming zone consisting of a semiconductor, a charge memory layer (6) with several stacked dielectric layers (6-1,2,3) and capable of storing charge. Two memory zones (6a,6b) have regions of the charge memory layer which overlap the two ends of the channel forming region, and a dielectric single-cell layer (4) contacts the channel forming region between the memory/storage regions. A control gate electrode (5) contacts the dielectric single-cell layer (4) and a memory gate electrode (7) contacts both memory regions and has regions which contact the memory regions which electrically inter-contact one another.

公开(公告)号：CA2315434C

公开(公告)日：2010-11-02

申请号：CA2315434

申请日：2000-07-27

Applicant: SONY CORP

Inventor： KUBOTA MICHITAKA ,  KOBAYASHI TOSHIO

IPC: G11C11/34 ,  G11C11/403 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/108

Abstract: A semiconductor device capable of reducing a cell area without affecting the accuracy, capable of reducing the number of interconnection layers, and capable of realizing a hybrid circuit of a memory cell and peripheral circuit easily and at a low cost, including a bit line, a word line, control gate line, a capacitor with a first electrode connected to the word line, a read transistor comprising an NMOS connected between the bit line and a predetermined potential point and with a gate electrode connected to a second electrode of a capacitor, and a write transistor comprising an NMOS connected between the bit line and the second electrode of the capacitor and with a gate electrode connected to the control gate line.

公开(公告)号：DE10292284T5

公开(公告)日：2004-04-22

申请号：DE10292284

申请日：2002-05-31

Applicant: SONY CORP

Inventor： TOMIIE HIDETO ,  TERANO TOSHIO ,  KOBAYASHI TOSHIO

IPC: H01L21/8247 ,  G11C16/04 ,  H01L21/28 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: To propose a new channel structure suitable for high efficiency source side injection, and provide a non-volatile semiconductor memory device and a charge injection method using the same. The non-volatile memory device includes a first conductivity type semiconductor substrate (SUB), a first conductivity type inversion layer-forming region (CH 1 ), second conductivity type accumulation layer-forming regions (ACLa, ACL 2 b), second conductivity type regions (S/D 1 , S/D 2 ), an insulating film (GD 0 ) and a first conductive layer (CL) formed on the inversion layer-forming region (CH 1 ). A charge accumulation film (GD) and a second conductive layer (WL) are stacked on an upper surface and side surface of the first conductive layer (CL), an exposure surface of the inversion layer-forming region (CH 1 ), and an upper surface of the accumulation layer-forming regions (ACLa, ACLb) and the second conductivity type regions (S/D 1 , S/D 2 ). The second conductive layer (WL) is connected to a word line and second conductivity type regions (S/D 1 , S/D 2 ) are connected to bit lines (Bla, BLb).

公开(公告)号：DE10213556A1

公开(公告)日：2002-10-17

申请号：DE10213556

申请日：2002-03-26

Applicant: SONY CORP

Inventor： AOYAMA JUNICHI ,  KOBAYASHI TOSHIO

IPC: H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor device comprises a gap (35) formed between wirings (32A, 32B, 32C) on a substrate. The gap is filled with gas having a thermal conductivity equal to or higher than three times of air at 0 deg C. An Independent claim is included for a wiring forming method in a semiconductor device which comprises: (i) forming a wiring and filling layer filled with wirings on a substrate; (ii) forming a gas permeable film on the wiring and filling layer; (iii) removing the filling layer through the gas permeable film to form a gap between the wirings; (iv) filling a gas having a thermal conductivity equal or higher than three times that of air at 0 deg C through the gas permeable film into gap; and (v) forming a gas impermeable film on the gas permeable film.

公开(公告)号：CA2306002A1

公开(公告)日：2000-10-26

申请号：CA2306002

申请日：2000-04-18

Applicant: SONY CORP

Inventor： HAYASHI YUTAKA ,  KOBAYASHI TOSHIO ,  MUKAI MIKIO

IPC: H01L27/10 ,  G11C11/405 ,  G11C11/407 ,  H01L27/085

Abstract: A semiconductor memory cell comprising a first transistor for readout, a second transistor for switching, and having a first region, a second region formed in a surface region of the first region, a third region formed in a surface region of the second region, a fourth region formed in a surface region of the first region and spaced from the second region, a fifth region formed in a surface region of the fourth region, and a gate region, wherein when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.

公开(公告)号：DE10194689B4

公开(公告)日：2011-07-28

申请号：DE10194689

申请日：2001-10-25

Applicant: SONY CORP

Inventor： MORIYA HIROYUKI ,  KOBAYASHI TOSHIO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: Nichtflüchtiger Halbleiterspeicher mit einer Speicherzelle, die Folgendes aufweist: – einen Kanalbildungsbereich (CH) aus einem Halbleiter; – Ladungsspeicherfilme (CSF) jeweils aus einer Anzahl aufeinander gestapelter dielektrischer Filme mit Ladungshaltevermögen; – zwei Speicher aus Bereichen der Ladungsspeicherfilme (CSF), die zwei Enden des Kanalbildungsbereichs (CH) überlappen; – einen einschichtigen dielektrischen Film (DF2), der mit dem Kanalbildungsbereich (CH) zwischen den Speichereinheiten in Kontakt steht; – zwei erste Steuerelektroden (CG1, CG2), von denen jeweils eine einer Speichereinheit so zugeordnet ist, und die so ausgebildet sind, dass ihre Breite mit zunehmendem Abstand von dem Kanalbildungsbereich abnimmt; und – eine zweite Steuerelektrode (WL), die in den Raum zwischen den zwei ersten Steuerelektroden (CG1, CG2) in einem gegen die ersten Steuerelektroden (CG1, CG2) isolierten Zustand eingebettet ist, wobei sie mit dem einschichtigen dielektrischen Film (DF2) in Kontakt steht.

公开(公告)号：CA2315434A1

公开(公告)日：2001-01-29

申请号：CA2315434

申请日：2000-07-27

Applicant: SONY CORP

Inventor： KOBAYASHI TOSHIO ,  KUBOTA MICHITAKA

IPC: G11C11/34 ,  G11C11/403 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/108

Abstract: A semiconductor device capable of reducing a cell area without affecting the accuracy, capable of reducing the number of interconnection layers, and capable of realizing a hybrid circuit of a memory cell and peripheral circuit easily and at a low cost, including a bit line, a word line, control gate line, a capacitor with a first electrode connected to the word line, a read transistor comprising an NMOS connected between the bit line and a predetermined potential point and with a gate electrode connected to a second electrode of a capacitor, and a write transistor comprising an NMOS connected between the bit line and the second electrode of the capacitor and with a gate electrode connected to the control gate line.

公开(公告)号：DE10194689T1

公开(公告)日：2003-10-16

申请号：DE10194689

申请日：2001-10-25

Applicant: SONY CORP

Inventor： MORIYA HIROYUKI ,  KOBAYASHI TOSHIO

IPC: H01L21/8247 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2 contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1 and BL2) formed on two impurity regions S/D, two first control electrodes CG1 and CG2 formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1 and CG2 in a space between them and contacting the single-layer dielectric film DF2. Since the main regions on facing surfaces of the first control electrodes CG1 and CG2 become forward tapered, conductive residue is not left at the time of processing the second control electrode WL.

公开(公告)号：JP2003203998A

公开(公告)日：2003-07-18

申请号：JP2002000380

申请日：2002-01-07

Applicant: SONY CORP

Inventor： TOMIYA HIDETO ,  KOBAYASHI TOSHIO

IPC: G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To solve the problem that the so-called source side injection type memory element has large power consumption for writing, delay of write pulses, and unread pits influenced during reading. SOLUTION: For example, when writing or erasure is carried out, a specified drain voltage Vd is applied to a source-drain region (BLa) on the side of a 1st electrode MGa on a laminated film GD having charge storage capability, on the basis of a source-drain region (BLb) on the side of a 2nd gate CG on a dielectric film GDO of a single layer, having no charge storage capability. Then a 1st gate voltage Vmg is applied to the 1st gate electrode MGa, and a 2nd gate voltage Vcg begins to be applied in the middle of the injection so that electric charges excited in terms of energy in a channel-forming region CH1 below nearby the space between gate electrodes are injected into the laminated film GD below the 1st gate electrode MGa from the source side. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003168750A

公开(公告)日：2003-06-13

申请号：JP2002007085

申请日：2002-01-16

Applicant: SONY CORP

Inventor： NAKAMURA AKIHIRO ,  NOMOTO KAZUMASA ,  FUJIWARA ICHIRO ,  TERANO TOSHIO ,  KOBAYASHI TOSHIO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide an isolation structure between word lines, which permits the lines to be arranged close. SOLUTION: The semiconductor device is provided with a plurality of memory transistors arranged in lines and a plurality of word lines WL1, WL2,..., being gate electrodes of the memory transistors in the same line and long in the direction of the lines and repeated in the direction of a row, while two word lines, neighbored in the direction of the row among the plurality of word lines, are separated by a dielectric film GD2 interposed so that the size in the separating direction of them becomes the thickness of the film. The dielectric film GD2 is constituted of a plurality of dielectric films BTM, CHS, TOP, for example, and is a charge accumulation film having charge retaining ability. COPYRIGHT: (C)2003,JPO