-
公开(公告)号：DE60037631D1
公开(公告)日：2008-02-14
申请号：DE60037631
申请日：2000-11-15
Applicant: SONY CORP
Inventor： ICHIKAWA TAKAHIRO , ISHIDA TAKAYUKI , SHIMIZU YOSHINORI
IPC: H04N5/76 , H04N5/783 , G11B20/10 , H04N5/85 , H04N5/92 , H04N5/93 , H04N9/804 , H04N9/877 , H04N9/888
Abstract: In a data reproduction technique, the throughput required for rapid reproduction or other special types of reproduction is improved, as is the data access speed at the time of rapid reproduction. In order to achieve these objectives, a system controller (19) is operable so that the address information of the MPEG data reproduced by a pickup (2) may be used to create the first reproduction control information at a sector detection circuit (4). The second reproduction control information corresponding to the starting point of pictures contained in the MPEG data destined to be reproduction signals by the first reproduction control signal and subjected to error correction in an error correction circuit (7) may be created in a stream detection circuit (9). Some MPEG data out of the entire MPEG data may be outputted for a rapid reproduction by referring to the second reproduction control information, and through these steps, the interval of reproducing I pictures in a rapid reproduction by using, for example, only I pictures is reduced and smooth reproduction is achieved.
-
公开(公告)号：DE68910596T2
公开(公告)日：1994-03-03
申请号：DE68910596
申请日：1989-07-03
Applicant: SONY CORP
Inventor： ICHIKAWA TAKAHIRO , FUJIKAWA MITSUNOBU , TAKESHIMA YASUO
Abstract: A scanconverter system with a superimposing apparatus for converting an interlaced video signal to a non-interlaced video signal and forming desired image data by superimposing a computer generated image on another image reproduced from a laser disc or the like. The system comprises a write clock generator for generating a write clock of a predetermined frequency, a read clock generator for generating a read clock of a double frequency, a line memory unit (3) for storing a horizontal line of an interlaced digital video signal and outputting a first non-interlaced digital video signal, a frame memory unit (8) for storing a frame of the interlaced digital video signal and outputting a second non-interlaced digital video signal, a detector (10) for detecting whether the interlaced digital video signal represents a still picture or not, and a selector (9) for selecting one of the first and second non-interlaced digital video signals according to the output of the detector. Selection of the first or second non-interlaced digital video signal depends on whether the interlaced digital video signal represents a still picture or not.
-
公开(公告)号：DE69622360T2
公开(公告)日：2003-03-27
申请号：DE69622360
申请日：1996-12-24
Applicant: SONY CORP
Inventor： ICHIKAWA TAKAHIRO
IPC: H04N5/92 , G11B20/18 , H03M13/00 , H03M13/29 , H04N5/783 , H04N5/85 , H04N7/24 , H04N9/804 , H04N9/877 , H04N19/00 , H04N19/102 , H04N19/152 , H04N19/166 , H04N19/196 , H04N19/42 , H04N19/423 , H04N19/426 , H04N19/44 , H04N19/46 , H04N19/503 , H04N19/65 , H04N19/67 , H04N19/70 , H04N19/89
Abstract: Digital signal decoder which decodes coded data, for example, a coded digital video signal, that has error-correcting data such as C1/C2 convolutional Reed-Solomon type data added thereto. The decoder stores in a memory the coded data, detects correctable errors in the stored coded data, ascertains positions of the detected errors in the coded data, and supplies error correction patterns that correspond to those errors. A second memory stores the ascertained positions of the errors as well as the error correction patterns, and coded data that correspond to the positions of the errors are read from the first memory and decoded by using the error correction patterns stored in the second memory so as to produce corrected decoded data. A digital signal reproducing apparatus embodying the above decoder also is disclosed.
-
公开(公告)号：DE69622360D1
公开(公告)日：2002-08-22
申请号：DE69622360
申请日：1996-12-24
Applicant: SONY CORP
Inventor： ICHIKAWA TAKAHIRO
IPC: H04N5/92 , G11B20/18 , H03M13/00 , H03M13/29 , H04N5/783 , H04N5/85 , H04N7/24 , H04N9/804 , H04N9/877 , H04N19/00 , H04N19/102 , H04N19/152 , H04N19/166 , H04N19/196 , H04N19/42 , H04N19/423 , H04N19/426 , H04N19/44 , H04N19/46 , H04N19/503 , H04N19/65 , H04N19/67 , H04N19/70 , H04N19/89
Abstract: Digital signal decoder which decodes coded data, for example, a coded digital video signal, that has error-correcting data such as C1/C2 convolutional Reed-Solomon type data added thereto. The decoder stores in a memory the coded data, detects correctable errors in the stored coded data, ascertains positions of the detected errors in the coded data, and supplies error correction patterns that correspond to those errors. A second memory stores the ascertained positions of the errors as well as the error correction patterns, and coded data that correspond to the positions of the errors are read from the first memory and decoded by using the error correction patterns stored in the second memory so as to produce corrected decoded data. A digital signal reproducing apparatus embodying the above decoder also is disclosed.
-
5.发明专利
公开(公告)号：MY129975A
公开(公告)日：2007-05-31
申请号：MYPI9700225
申请日：1997-01-22
Applicant: SONY CORP
Inventor： ICHIKAWA TAKAHIRO , MASUDA SHOZO , YASUDA KAZUHIRO , SATO SHIGEHARU
Abstract: ERROR CORRECTION DECODING APPARATUS (726) DECODES ERROR CORRECTION ENCODED DATA REPRODUCED FROM A RECORDING MEDIUM (104) BY DECODING THE ENCODED DATA TO PRODUCE DECODED DATA IN FRAME UNITS AND BY GENERATING DECODING INFORMATION IN FRAME UNITS; THE DECODED DATA AND DECODING INFORMATION ARE STORED IN CORRESPONDENCE BY FRAME UNIT AND THE DECODED DATA AND DECODING INFORMATION ARE RETRIEVED FROM STORAGE WHILE FRAME SYNCHRONIZING WITH ADDRESS DATA REPRESENTING A PHYSICAL LOCATION OF THE ENCODED DATA ON THE RECORDING MEDIUM (104).(FIG 7)
-
Patent Agency Ranking
公开(公告)号：MY127448A
公开(公告)日：2006-12-29
申请号：MYPI20005351
申请日：2000-11-15
Applicant: SONY CORP
Inventor： ICHIKAWA TAKAHIRO , ISHIDA TAKAYUKI , SHIMIZU YOSHINORI
IPC: H04N5/76 , G11B20/10 , H04N5/783 , H04N5/85 , H04N5/92 , H04N5/93 , H04N9/804 , H04N9/877 , H04N9/888
Abstract: THE OBJECTIVES OF THE PRESENT INVENTION ARE TO REDUCE THE THROUGHPUT REQUIRED FOR A RAPID REPRODUCTION OR OTHER SPECIAL TYPES OF REPRODUCTION AND TO IMPROVED ALSO THE DATA ACCESS SPEED AT THE TIME OFA RAPID REPRODUCTION. IN ORDER TO ACHIEVE THESE OBJECTIVES, THE SYSTEM CONTROLLER (19) CONTROLS SO THAT THE ADDRESS INFORMATION OF THE MPEG DATA REPRODUCED BY A PICKUP (2) MAY BE USED TO CREATE THE FIRST REPRODUCTION CONTROL INFORMATION AT A SECTOR DETECTION CIRCUIT (4), THAT THE SECOND REPRODUCTION CONTROL INFORMATION CORRESPONDING TO THE STARTING POINT OF PICTURES CONTAINED IN THE MPEG DATA DESTINED TO BE REPRODUCTION SIGNALS BY THE FIRST REPRODUCTION CONTROL SIGNAL AND SUBJECTED TO AN ERROR CORRECTION IN AN ERROR CORRECTION CIRCUIT (7) MAY BE CREATED IN A STREAM DETECTION CIRCUIT (9), AND THAT SOME MPEG DATA OUT OF THE ENTIRE MPEG DATA MAY BE OUTPUTTED FOR A RAPID REPRODUCTION BY REFERRING TO THE SECOND REPRODUCTION CONTROL INFORMATION, AND THROUGH THESE STEPS, THE INTERVAL OF REPRODUCING 1 PICTURES IN A RAPID REPRODUCTION BY USING FOR EXAMPLE ONLY 1 PICTURES IS REDUCED AND A SMOOTH REPRODUCTION IS ACHIEVED. (FIGURE 6).
-
公开(公告)号：MY115663A
公开(公告)日：2003-08-30
申请号：MYPI9605436
申请日：1996-12-23
Applicant: SONY CORP
Inventor： ICHIKAWA TAKAHIRO
IPC: G11B20/18 , H04N5/92 , H03M13/00 , H03M13/29 , H04N5/783 , H04N5/85 , H04N7/24 , H04N9/804 , H04N9/877 , H04N19/00 , H04N19/102 , H04N19/152 , H04N19/166 , H04N19/196 , H04N19/42 , H04N19/423 , H04N19/426 , H04N19/44 , H04N19/46 , H04N19/503 , H04N19/65 , H04N19/67 , H04N19/70 , H04N19/89
Abstract: DIGITAL SIGNAL DECODER (52) WHICH DECODES CODED DATA, FOR EXAMPLE, A CODED DIGITAL VIDEO SIGNAL, THAT HAS ERROR-CORRECTING DATA SUCH AS C1/C2 CONVOLUTIONAL REED-SOLOMON TYPE DATA ADDED THERETO. THE DECODER (52) STORES IN A MEMORY (51) THE CODED DATA, DETECTS CORRECTABLE ERRORS IN THE STORED CODED DATA, ASCERTAINS POSITIONS OF THE DETECTED ERRORS IN THE CODED DATA, AND SUPPLIES ERROR CORRECTION PATTERNS THAT CORRESPOND TO THOSE ERRORS. A SECOND MEMORY (53) STORES THE ASCERTAINED POSITIONS OF THE ERRORS AS WELL AS THE ERROR CORRECTION PATTERNS, AND CODED DATA THAT CORRESPOND TO THE POSITIONS OF THE ERRORS ARE READ FROM THE FIRST MEMORY (51) AND DECODED BY USING THE ERROR CORRECTION PATTERNS STORED IN THE SECOND MEMORY (53) SO AS TO PRODUCE CORRECTED DECODED DATA. A DIGITAL SIGNAL REPRODUCING APPARATUS EMBODYING THE ABOVE DECODER (52) ALSO IS DISCLOSED. (FIG.23)
-
公开(公告)号：DE60037631T2
公开(公告)日：2009-10-01
申请号：DE60037631
申请日：2000-11-15
Applicant: SONY CORP
Inventor： ICHIKAWA TAKAHIRO , ISHIDA TAKAYUKI , SHIMIZU YOSHINORI
IPC: H04N5/76 , H04N5/783 , G11B20/10 , H04N5/85 , H04N5/92 , H04N5/93 , H04N9/804 , H04N9/877 , H04N9/888
Abstract: In a data reproduction technique, the throughput required for rapid reproduction or other special types of reproduction is improved, as is the data access speed at the time of rapid reproduction. In order to achieve these objectives, a system controller (19) is operable so that the address information of the MPEG data reproduced by a pickup (2) may be used to create the first reproduction control information at a sector detection circuit (4). The second reproduction control information corresponding to the starting point of pictures contained in the MPEG data destined to be reproduction signals by the first reproduction control signal and subjected to error correction in an error correction circuit (7) may be created in a stream detection circuit (9). Some MPEG data out of the entire MPEG data may be outputted for a rapid reproduction by referring to the second reproduction control information, and through these steps, the interval of reproducing I pictures in a rapid reproduction by using, for example, only I pictures is reduced and smooth reproduction is achieved.
-
公开(公告)号：DE68910596D1
公开(公告)日：1993-12-16
申请号：DE68910596
申请日：1989-07-03
Applicant: SONY CORP
Inventor： ICHIKAWA TAKAHIRO , FUJIKAWA MITSUNOBU , TAKESHIMA YASUO
Abstract: A scanconverter system with a superimposing apparatus for converting an interlaced video signal to a non-interlaced video signal and forming desired image data by superimposing a computer generated image on another image reproduced from a laser disc or the like. The system comprises a write clock generator for generating a write clock of a predetermined frequency, a read clock generator for generating a read clock of a double frequency, a line memory unit (3) for storing a horizontal line of an interlaced digital video signal and outputting a first non-interlaced digital video signal, a frame memory unit (8) for storing a frame of the interlaced digital video signal and outputting a second non-interlaced digital video signal, a detector (10) for detecting whether the interlaced digital video signal represents a still picture or not, and a selector (9) for selecting one of the first and second non-interlaced digital video signals according to the output of the detector. Selection of the first or second non-interlaced digital video signal depends on whether the interlaced digital video signal represents a still picture or not.
-
10.发明专利
公开(公告)号：JP2006031842A
公开(公告)日：2006-02-02
申请号：JP2004210354
申请日：2004-07-16
Inventor： ICHIKAWA TAKAHIRO , IKEDA KIYOSHI , HAMADA TOSHIMICHI , TATSUMI SHINYA , YAMATO TETSUYA , KOGANEI RYOJI
Abstract: PROBLEM TO BE SOLVED: To correctly prevent recording of unreproducible data when receiving two or more kinds of data streams and recording them on a recording medium.
SOLUTION: A byte counter 41 always detects data length of input data group based on a synchronizing signal Sync_In. A stream discrimination section 71 discriminates types of data stream and existence of errors based on the detected data length. A frame counter 42 performs count up when the input data group is correct DV frame data based on the discrimination results of the stream discrimination section 71. When the input data group is error or a TS packet, the frame counter 42 does not perform count-up and a data transfer section 44 stops data transfer. A recording control section 72 transmits and records the number of pieces of frame data DV equivalent to the count Frame_Cnt of the frame counter 42 stored in a buffer control section 50 from the start time of recording in order to the recording medium.
COPYRIGHT: (C)2006,JPO&NCIPIAbstract translation: 要解决的问题：在接收两种或更多种数据流并将其记录在记录介质上时，正确地防止记录不可再生数据。 解决方案：字节计数器41总是基于同步信号Sync_In来检测输入数据组的数据长度。 流鉴别部分71基于检测到的数据长度来鉴别数据流的类型和存在错误。 帧计数器42基于流鉴别部分71的鉴别结果，当输入数据组为正确的DV帧数据时执行计数。当输入数据组为错误或TS分组时，帧计数器42不执行计数 - 数据传输部分44停止数据传送。 记录控制部分72从记录的开始时间开始并记录与记录的开始时间相对应的存储在缓冲器控制部分50中的帧计数器42的计数帧Cnt的帧数据数量DV的数量，以便记录到记录介质上。 版权所有（C）2006，JPO＆NCIPI
-
-
-
-
-
-
-
-
-
Search Results
33
records
(took 0.023 seconds)
