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公开(公告)号：DE68910596D1
公开(公告)日：1993-12-16
申请号：DE68910596
申请日：1989-07-03
Applicant: SONY CORP
Inventor： ICHIKAWA TAKAHIRO , FUJIKAWA MITSUNOBU , TAKESHIMA YASUO
Abstract: A scanconverter system with a superimposing apparatus for converting an interlaced video signal to a non-interlaced video signal and forming desired image data by superimposing a computer generated image on another image reproduced from a laser disc or the like. The system comprises a write clock generator for generating a write clock of a predetermined frequency, a read clock generator for generating a read clock of a double frequency, a line memory unit (3) for storing a horizontal line of an interlaced digital video signal and outputting a first non-interlaced digital video signal, a frame memory unit (8) for storing a frame of the interlaced digital video signal and outputting a second non-interlaced digital video signal, a detector (10) for detecting whether the interlaced digital video signal represents a still picture or not, and a selector (9) for selecting one of the first and second non-interlaced digital video signals according to the output of the detector. Selection of the first or second non-interlaced digital video signal depends on whether the interlaced digital video signal represents a still picture or not.
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公开(公告)号：DE60134440D1
公开(公告)日：2008-07-31
申请号：DE60134440
申请日：2001-02-09
Applicant: SONY CORP
Inventor： TAKESHIMA YASUO , KUBONO FUMIO , ABE HIROSHI , OMORI KAZUO , TSUYAMA FUMIO , NAKAYAMA HIROSHI
IPC: G07F19/00 , G07G1/12 , G06K17/00 , G06Q20/00 , G06Q20/06 , G06Q40/00 , G06Q40/02 , G07F7/08 , G07F7/10 , H04L29/06
Abstract: An electronic money system (1) terminates communication to a management center (3) indistinguishably from a case in which the communication to the management center (3) is completed within a predetermined period when it is impossible to complete the communication to the management center (3) within the predetermined period. By switching an operation mode, a predetermined portable terminal is used instead of a communication line to upload and download data. When it is impossible to obtain data required for processing through the communication line, processing is performed based on data possessed up until that time.
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公开(公告)号：DE68910596T2
公开(公告)日：1994-03-03
申请号：DE68910596
申请日：1989-07-03
Applicant: SONY CORP
Inventor： ICHIKAWA TAKAHIRO , FUJIKAWA MITSUNOBU , TAKESHIMA YASUO
Abstract: A scanconverter system with a superimposing apparatus for converting an interlaced video signal to a non-interlaced video signal and forming desired image data by superimposing a computer generated image on another image reproduced from a laser disc or the like. The system comprises a write clock generator for generating a write clock of a predetermined frequency, a read clock generator for generating a read clock of a double frequency, a line memory unit (3) for storing a horizontal line of an interlaced digital video signal and outputting a first non-interlaced digital video signal, a frame memory unit (8) for storing a frame of the interlaced digital video signal and outputting a second non-interlaced digital video signal, a detector (10) for detecting whether the interlaced digital video signal represents a still picture or not, and a selector (9) for selecting one of the first and second non-interlaced digital video signals according to the output of the detector. Selection of the first or second non-interlaced digital video signal depends on whether the interlaced digital video signal represents a still picture or not.
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公开(公告)号：SG145528A1
公开(公告)日：2008-09-29
申请号：SG2003056447
申请日：2001-01-30
Applicant: SONY CORP
Inventor： TAKESHIMA YASUO , KUBONO FUMIO , ABE HIROSHI , OMORI KAZUO , TSUYAMA FUMIO , NAKAYAMA HIROSHI
IPC: G07G1/12 , G06K17/00 , G06Q20/00 , G06Q20/06 , G06Q40/00 , G06Q40/02 , G07F7/08 , G07F7/10 , H04L29/06
Abstract: An electronic money transaction processing method is provided including an updating step of subtracting part of a payment amount from a portable electronic device that stores a value of electronic money and updating the amount of the electronic money stored in the portable electronic device. In a communicating step, the partially-paid amount is communicated to an external unit. Alternatively, the amount partially paid using the electronic money is subtracted from the payment amount, and the outstanding amount is communicated to the external unit.
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公开(公告)号：JPH02228889A
公开(公告)日：1990-09-11
申请号：JP5036889
申请日：1989-03-02
Applicant: SONY CORP
Inventor： ICHIKAWA TAKAHIRO , TAKESHIMA YASUO , FUJIKAWA MITSUNORI
Abstract: PURPOSE:To execute satisfactory picture processing even when there is jitter in an input video signal by writing the video signal to a memory in synchronism with the output signal of a first PLL circuit and reading the contents of the memory in synchronism with the output signal of a second PLL circuit. CONSTITUTION:A first PLL circuit 20 is provided to stop the output signal of a voltage control oscillator 23 according to an external control signal, namely, a stop signal STOP at a prescribed time and a normal second PLL circuit 8 is provided. The A/D-converted video signal is written to a memory 4 in synchronism with the output signal of the first PLL circuit 20 and the contents of the memory are read in synchronism with the output signal of the second PLL circuit 8. Thus, the satisfactory picture processing can be executed without being affected by the jitter even when there is the jitter in the input video signal. Since the exclusive PLL circuits are respectively provided on the side of writing and reading, the picture processing can be executed with much higher accuracy.
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Patent Agency Ranking
公开(公告)号：JPS57166656A
公开(公告)日：1982-10-14
申请号：JP5032981
申请日：1981-04-03
Applicant: SONY CORP
Inventor： TAKESHIMA YASUO , MATSUMOTO YOSHIHIKO
Abstract: PURPOSE:To expand the spaces of memory addresses by using the combination of a specific instruction and an optional instruction to decode the specific instruction and control the switching of a memory bank. CONSTITUTION:Combination data of a specific instruction and an optional instruction in an ROM4 are fetched into a latch 8, an output from the latch 8 and bits D0 and D1 are applied to a timing circuit 9 and, at the detection of the specific instruction, an RAM6 is switched to an RAM7. The entitled circuit is provided with also a counter 11 and a memory 12 and the switching between the RAMs 6 and 7 is stored in the memory 12. The counted value of the counter 11 is advanced by 1 at the time of a call instruction and is subtracted by 1 from the counted value at the time of a return instruction; the output from the counter 11 is discriminated as the address in the memory 12. Thus, the switching command of a switching circuit 10 is written in the memory 12 or the contents of the memory 12 are read out. In case of the return instruction, the contents read out from the memory 12 are sent to a timing circuit 9 and a correct switching command is outputted from the circuit 10.
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公开(公告)号：JPS5342622A
公开(公告)日：1978-04-18
申请号：JP11782276
申请日：1976-09-30
Applicant: SONY CORP
Inventor： OOMICHI YASUYUKI , TAKESHIMA YASUO , SAKAI KOUICHI
IPC: H01J29/76
Abstract: PURPOSE:Horizontal deflecting width and vertical deflecting width of an electron beam at the neck part side are made nearly equal each other, thereby preventing the miss-convergence without providing a specific device.
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公开(公告)号：JP2001022381A
公开(公告)日：2001-01-26
申请号：JP19712299
申请日：1999-07-12
Applicant: SONY CORP
Inventor： TAKESHIMA YASUO
Abstract: PROBLEM TO BE SOLVED: To automatically and inexpensively adjust the volume of on-vehicle audio equipment. SOLUTION: A TV/audio part 16 takes out an audio signal from the loaded audio equipments. An electronic volume part 17 adjusts the output level of the audio signal according to a control signal of a control signal line C1. An amplifier part 18 amplifies the audio signal output from the electronic volume means. A microphone 11 converts a calling sound of communication equipments to a voice signal. The amplifier part 12 amplifies the voice signal from the microphone 11. A speech recognition part 13 outputs the control signal to the control signal line C1 when the output speech signal from the amplifier part 12 is the prescribed voice signal. A part of the audio signal is taken into the amplifier part 12 through an attenuator part 14 and a delay part 15 to enhance a recognition rate.
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公开(公告)号：JPH02149184A
公开(公告)日：1990-06-07
申请号：JP30328388
申请日：1988-11-30
Applicant: SONY CORP
Inventor： ICHIKAWA TAKAHIRO , TAKESHIMA YASUO , FUJIKAWA MITSUNORI , TATSUMI IZURU
Abstract: PURPOSE:To attain gain lock quickly and accurately by quickening locking of a horizontal synchronizing signal while interleaving the horizontal synchronizing signal by intention, and locking the horizontal synchronizing signal and the vertical synchronizing signal. CONSTITUTION:The phase of a horizontal synchronizing signal H21 of a video signal generated by a video signal generating circuit based on an external synchronizing signal and a horizontal synchronizing signal H11 of a reference composite synchronizing signal are compared by a phase comparator circuit 29. When the phase difference exceeds 1H, the horizontal synchronizing signal H11 or H21 in the reference composite synchronizing signal or the synchronizing signal of the video signal is interleaved. Thus, the voltage level fed to a VCO 31 is changed and a signal in an oscillated frequency in response to the voltage level is outputted and used as an external synchronizing signal, then the period of the synchronizing signal of the video signal is changed based thereupon and the synchronizing signal of the video signal is locked to the phase of the reference composite synchronizing signal. Thus, the gain lock is implemented quickly and accurately.
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公开(公告)号：JPS60205898A
公开(公告)日：1985-10-17
申请号：JP6185884
申请日：1984-03-29
Applicant: SONY CORP
Inventor： TAKESHIMA YASUO , OOTA MASAHIRO
IPC: G11C11/406 , G11C11/34
Abstract: PURPOSE:To attain the satisfactory refresh with a simple constitution by performing the refresh and access of one time, etc. according to a refresh mode and repeating these refresh and access actions until the access frequency reaches a prescribed level. CONSTITUTION:The refresh of a RAM20 is started by a prescribed row address strobe RAS obtained by synthesization of the refresh interval and a memory access end signal via a NAND circuit IC17 to which the output signal TMR of a refresh period produced by a timer, a D type FFIC16, an AND circuit IC2 to which the write and read control signals are supplied, an OR circuit IC9, etc. Then the refresh of one time is carried out for each access by a buffer IC22 together with an access carried out by a selector IC23. When these actions are repeated and the refresh frequency reaches a prescribed level, an FFIC16 is cleared through a counter IC21. Then only the accesses are carried out until the end of the subsequent refresh period. Thus the satisfactory refresh is secured through a simple constitution with reduced queuing for access.
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