公开(公告)号：EP1865714A4

公开(公告)日：2010-12-15

申请号：EP06714748

申请日：2006-02-27

Applicant: SONY CORP

Inventor： KINUGASA YUKIHISA ,  SEGAMI MASAHIRO ,  HIROTA ISAO

IPC: H01L21/339 ,  H01L27/148 ,  H01L29/762 ,  H04N5/335 ,  H04N5/372 ,  H04N5/376

CPC classification number: H04N5/3728 ,  G09G2330/021 ,  G09G2330/024 ,  H04N5/372 ,  H04N5/37206 ,  H04N5/376 ,  H04N5/3765

公开(公告)号：JP2008053992A

公开(公告)日：2008-03-06

申请号：JP2006227391

申请日：2006-08-24

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KINUGASA YUKIHISA

IPC: H03K19/0185 ,  G09G3/20 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To provide a boosting type level shifting circuit with the improved hot carrier robustness. SOLUTION: A series circuit of resistance elements R106_a and R106_b is arranged between each of the drains of a transistor Q101 at an input stage and a transistor Q103 at an output stage. The series circuit is also used as a feedback signal acquiring portion 105. A signal acquired by a connection node N106 of one of resistance elements R106_a and R106_b is adopted as a feedback signal SFB to the gate of the transistor Q103 of another side at the output stage. When the resistances element R106_a and R106_b are arranged as above, voltage between the drain and the source of the transistor Q101 can be reduced to a small value by utilizing potential difference based on an operating current at the time of switching operation, thereby, the hot carrier robustness can be improved. In addition, since a positive feedback loop from a shallow voltage level of the connection node N106 can be formed, a quick response can be obtained. Since a pinch-off region can be quickly got through, the hot carrier robustness can be improved. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供具有改进的热载体稳健性的升压型电平移位电路。 解决方案：电阻元件R106_a和R106_b的串联电路布置在输入级的晶体管Q101的每个漏极和输出级的晶体管Q103之间。 串联电路也用作反馈信号获取部分105.由电阻元件R106_a和R106_b之一的连接节点N106获取的信号作为反馈信号SFB被用作输出端的另一侧的晶体管Q103的栅极 阶段。 当电阻元件R106_a和R106_b如上所述排列时，通过利用基于切换操作时的工作电流的电位差，晶体管Q101的漏极和源极之间的电压可以减小到较小的值，因此，热 可以提高载波稳健性。 此外，由于可以形成从连接节点N106的浅电平电平的正反馈回路，因此可以获得快速响应。 由于夹紧区域可以快速通过，因此可以提高热载体的鲁棒性。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2014170811A

公开(公告)日：2014-09-18

申请号：JP2013041030

申请日：2013-03-01

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KINUGASA YUKIHISA ,  FURUSAWA TOSHIHIRO ,  KABAYA YOSHITERU ,  HIGASHITSUTSUMI YOSHIHITO

IPC: H01L23/12 ,  H01L27/14 ,  H01Q23/00

CPC classification number: H01L27/14618 ,  H01L23/66 ,  H01L27/14636 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/014

Abstract: PROBLEM TO BE SOLVED: To respond to needs of further increase in capacity, further miniaturization, and further power saving in electronic equipment.SOLUTION: A CSP (Chip Size Package) has an antenna for wireless communication related to signal transmission/reception with an external substrate. The antenna is formed as distribution wires of a re-wiring layer arranged between a silicon layer and a solder bump.

Abstract translation: 要解决的问题：满足电子设备进一步增加容量，进一步小型化和进一步节电的需求。解决方案：CSP（芯片尺寸封装）具有与外部信号发送/接收相关的无线通信天线 基质。 天线形成为布置在硅层和焊料凸块之间的再布线层的配线。

公开(公告)号：JP2008092422A

公开(公告)日：2008-04-17

申请号：JP2006272888

申请日：2006-10-04

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KINUGASA YUKIHISA

IPC: H03M1/78 ,  H03M1/68

Abstract: PROBLEM TO BE SOLVED: To improve the linearity of a resistor ladder type DAC circuit by the reduction of uncontrollable factors such as a resistance element, regarding the resistor ladder type DAC circuit.
SOLUTION: The resistor ladder circuit comprises: a serial resistor group on a high voltage side for which a plurality of resistors are serially connected between a voltage supply terminal and a voltage take-out terminal and the plurality of resistors are set to a specified ratio; a switch group on the high voltage side respectively connected between the connection points of the respective resistors of the serial resistor group on the high voltage side and the voltage take-out terminal; a serial resistor group on a low voltage side for which the plurality of resistors are serially connected to the voltage take-out terminal and the plurality of resistors are respectively set to the specified ratio; a switch group on the low voltage side respectively connected between the connection points of the respective resistors of the serial resistor group on the low voltage side and a reference potential; and a control circuit for switching the connection points of the respective resistors of the serial resistor groups on the high voltage and low voltage sides by the switch groups on the high voltage and low voltage sides and performing switch control so that a composite resistance value does not overlap. By reducing the number of resistors, the randomness of resistance value dispersion is reduced.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：关于电阻梯型DAC电路，通过减少诸如电阻元件的不可控因素来提高电阻梯型DAC电路的线性度。 解决方案：电阻梯形电路包括：高电压侧的串联电阻器组，多个电阻串联连接在电压端和电压取出端之间，多个电阻被设定为 指定比例 高压侧的开关组分别连接在高电压侧的串联电阻器组的各个电阻器的连接点和电压取出端子之间; 分别将多个电阻器串联连接到电压取出端子和多个电阻器的低电压侧的串联电阻器组设定为规定的比率; 低电压侧的开关组分别连接在低电压侧的串联电阻器组的各个电阻器的连接点和参考电位之间; 以及控制电路，用于通过高压侧和低压侧的开关组切换高压侧和低压侧的串联电阻体的各个电阻体的连接点，进行开关控制，使得复合电阻值不 交叠。 通过减少电阻数量，减小了电阻值色散的随机性。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2013200366A

公开(公告)日：2013-10-03

申请号：JP2012067290

申请日：2012-03-23

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FURUSAWA TOSHIHIRO ,  HIGASHITSUTSUMI YOSHIHITO ,  KABAYA YOSHITERU ,  KINUGASA YUKIHISA ,  KAWABE HIDEO ,  ISHIDA TAKEHISA ,  KATO YUSAKU ,  NAGAI NOBUYUKI ,  MORITA MASAYOSHI ,  YAMAGISHI HIROYUKI

IPC: G02B7/28 ,  G02B7/04 ,  G03B3/04 ,  G03B13/32 ,  H04N5/225 ,  H04N5/232 ,  H04N5/335

CPC classification number: H04N5/2257 ,  G02B7/08 ,  G03B3/04 ,  G03B2205/0053 ,  H04N5/2253 ,  H04N5/2254 ,  H04N5/23212

Abstract: PROBLEM TO BE SOLVED: To provide a camera module and a camera which enable movement of an image sensor and also enable large lenses with large-aperture lenses, zooming or the like to be mounted.SOLUTION: An actuator unit comprises: a movable joint part to which one end of an imaging element is secured and which is movable in response to back-and-forth movement; a parallel link mechanism part, one end of which is mounted on the movable joint part while the other end of which is secured, and which holds the imaging element at a target position synchronized with movement of the movable joint part; and a needle, one end of which is joined so as to allow transmission of displacement motion in relation to a joined area between the movable joint part and the one end of the parallel link mechanism part, and which is displaced by a displacement corresponding to a level of applied driving voltage, to cause the imaging element to move back and forth between a first position and a second position in the optical axis direction.

Abstract translation: 要解决的问题：提供一种能够使图像传感器移动的相机模块和照相机，并且还能够安装具有大孔径透镜，变焦等的大型透镜。解决方案：致动器单元包括：可动接头部分 成像元件的一端被固定到其上并可响应往复运动而移动; 平行连杆机构部分，其一端安装在可动接头部分上，同时其另一端固定，并将成像元件保持在与可动接头部分的运动同步的目标位置; 以及针，其一端被接合以便允许相对于可动接头部分和平行连杆机构部分的一端之间的接合区域的位移运动的传递，并且被移位相当于 施加的驱动电压的电平，使得成像元件在光轴方向上的第一位置和第二位置之间来回移动。

公开(公告)号：JP2007221403A

公开(公告)日：2007-08-30

申请号：JP2006038795

申请日：2006-02-16

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KAWABE AZUMA ,  KAKIOKA HIDENOBU ,  FUKUOKA FUMIAKI ,  HIROTA ISAO ,  SEGAMI MASAHIRO ,  KINUGASA YUKIHISA

IPC: H01L27/148 ,  H04N5/335 ,  H04N5/341 ,  H04N5/365 ,  H04N5/369 ,  H04N5/3728 ,  H04N5/376

CPC classification number: H04N5/3765 ,  H04N5/372 ,  H04N5/37213

Abstract: PROBLEM TO BE SOLVED: To reduce interference between two or more drive voltages applied to a load such as a CCD.
SOLUTION: A drive circuit has a driving mode for outputting current from a certain reference current through current mirror circuits CM1, CM2 when two or more drive voltages are applied to the load such as a CCD, and the current is slowly switched at a certain optional time constant by time constant circuits 540, 541. Consequently, the transient speed of voltage Vout which is a drive voltage is decreased and the interference between the drive voltages is reduced.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：减少施加到诸如CCD的负载的两个或更多个驱动电压之间的干扰。 解决方案：当将两个或多个驱动电压施加到诸如CCD的负载时，驱动电路具有用于从某一参考电流输出电流通过电流镜电路CM1，CM2的驱动模式，并且电流缓慢地切换 通过时间常数电路540,541的一定的可选时间常数。因此，作为驱动电压的电压Vout的瞬态速度降低，并且驱动电压之间的干扰减小。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2014017575A

公开(公告)日：2014-01-30

申请号：JP2012152173

申请日：2012-07-06

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KINUGASA YUKIHISA

IPC: H03K17/687

Abstract: PROBLEM TO BE SOLVED: To provide a circuit for driving a capacitive load, a method for driving a capacitive load, and a camera module having the circuit for driving a capacitive load which drive a capacitive load whose capacitance value nonlinearly varies with varying temperature, in an optimum condition matching an environmental temperature condition.SOLUTION: The disclosed circuit for driving a capacitive load which is adapted to drive a capacitive load whose capacitance value nonlinearly changes with temperature, and can calibrate a driving force for driving the capacitive load includes: a temperature range detection section for detecting a temperature range in a usage environment of the capacitive load; and a control section for controlling the frequency of calibrating the driving force for the capacitive load in accordance with the temperature range detected by the temperature range detection section.

Abstract translation: 要解决的问题：提供用于驱动电容性负载的电路，用于驱动电容性负载的方法，以及具有用于驱动容性负载的电路的照相机模块，所述电容负载驱动电容值随着温度变化而非线性变化的电容性负载， 与环境温度条件匹配的最佳条件。解决方案：用于驱动电容性负载的公开电路，其适于驱动电容值随温度非线性变化的电容性负载，并且可以校准用于驱动电容性负载的驱动力包括：温度 距离检测部，用于检测所述电容性负载的使用环境中的温度范围; 以及控制部分，用于根据由温度范围检测部分检测到的温度范围控制校准电容性负载的驱动力的频率。

公开(公告)号：JP2010118860A

公开(公告)日：2010-05-27

申请号：JP2008290189

申请日：2008-11-12

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KIKUCHI HIDEKAZU ,  ICHIMURA HAJIME ,  KINUGASA YUKIHISA

IPC: H03F1/26

CPC classification number: H03F3/45273 ,  G05F3/262

Abstract: PROBLEM TO BE SOLVED: To provide a differential output circuit capable of preventing generation of common-mode noise, and to provide a communication device. SOLUTION: This differential output circuit includes first and second current mirror circuits 11, 12 that provide the gates of slave-side transistors Q12, Q14 with gate voltages of master-side transistors Q11, Q13 via voltage followers A11, A12 where a slew rate at a rise time is equal to that at a fall time. Thus, when the master-side current is increased or decreased by providing the gates of the slave-side transistors Q12, Q14 with the gate voltages of master-side transistors Q11, Q13 via the voltage followers A11, A12 where the slew rate at a rise time is equal to that at a fall time, an incremental change in slave-side current and a decremental change in slave-side current are made symmetrical with each other. The use of such current mirrors in a differential manner leads to no generation of common-mode noise even in these changes. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供能够防止产生共模噪声的差分输出电路，并提供通信装置。 解决方案：该差分输出电路包括第一和第二电流镜电路11,12，其通过电压跟随器A11，A12向主侧晶体管Q12，Q14的栅极提供主端晶体管Q11，Q13的栅极电压，其中a 上升时间的压摆率等于下降时间。 因此，当通过经由电压跟随器A11，A12的主端晶体管Q11，Q13的栅极电压提供从侧晶体管Q12，Q14的栅极来增大或减小主端电流，其中a侧的压摆率 上升时间等于下降时间，从侧电流的增量变化和从侧电流的减量变化相互对称。 以这种差分方式使用这种电流镜子即使在这些变化中也不会产生共模噪声。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2006311483A

公开(公告)日：2006-11-09

申请号：JP2005294398

申请日：2005-10-07

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KINUGASA YUKIHISA ,  SEGAMI MASAHIRO ,  HIROTA ISAO

IPC: H01L21/339 ,  H01L27/148 ,  H01L29/762 ,  H04N5/335 ,  H04N5/372 ,  H04N5/376

CPC classification number: H04N5/3728 ,  G09G2330/021 ,  G09G2330/024 ,  H04N5/372 ,  H04N5/37206 ,  H04N5/376 ,  H04N5/3765

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption in a drive device for driving a capacitive element such as a charge coupled device.
SOLUTION: A driver circuit is connected so as to configure a triphase LC resonance circuit among three element electrodes. Three nodes Node-A, Node-B, Node-C of the triphase LC resonance circuit are driven by any one of logic level 0, high impedance Z and 1 so that LC resonance circuits constituting the triphase LC resonance circuit resonate while sequentially shifting phases. By driving each of the phases to keep a phase difference of 2π/3, an output logic takes any one of 0, high impedance and 1 and phases and logics are allocated so as not to overlap with each other in any timing at any point of time.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了降低用于驱动诸如电荷耦合器件的电容元件的驱动装置中的功耗。

解决方案：连接驱动电路，以便在三个元件电极之间配置三相LC谐振电路。 三相LC谐振电路的三个节点A，节点B，节点C由逻辑电平0，高阻抗Z和1中的任何一个驱动，使得构成三相LC谐振电路的LC谐振电路在顺序移相 。 通过驱动每个相位以保持2π/ 3的相位差，输出逻辑采用0，高阻抗和1中的任何一个，并且分配相位和逻辑，使得在任何时间点的任何时刻不分配彼此重叠 时间。 版权所有（C）2007，JPO＆INPIT