公开(公告)号：EP1211662A4

公开(公告)日：2003-02-05

申请号：EP01915834

申请日：2001-03-27

Applicant: SONY CORP

Inventor： NAKAJIMA YOSHIHARU ,  MAEKAWA TOSHIKAZU

IPC: G02F1/133 ,  G09G20060101 ,  G09G3/20 ,  G09G3/30 ,  G09G3/36 ,  H04M1/02 ,  H04M1/73

CPC classification number: G09G3/3688 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2310/04 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2330/022

Abstract: A liquid crystal display having a partial screen displaying mode, wherein a latch control circuit (17) stores white or black data which is color data for one line in latch circuits (121, 131) at the start of a video nondisplay period, repetitively reads the color data at 1-H cycle until the end of the display period, and outputs the color data to each column line of the display area (11) so as to stop the write of data in the latch circuits (121, 131) for almost the whole video nondisplaying period.

公开(公告)号：EP1343134A4

公开(公告)日：2008-07-09

申请号：EP01999936

申请日：2001-12-06

Applicant: SONY CORP

Inventor： NAKAJIMA YOSHIHARU ,  MAKI YASUHITO ,  MAEKAWA TOSHIKAZU

IPC: G09G3/20 ,  G09G3/30 ,  G09G3/36 ,  G02F1/133

CPC classification number: G09G3/2011 ,  G09G3/30 ,  G09G3/3677 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2300/0408 ,  G09G2300/08 ,  G09G2310/027 ,  G09G2310/0294 ,  G09G2310/06

Abstract: A timing generation circuit (15) is formed integrally on the same glass substrate (11) together with a display area section (12) similarly to an H driver (13U) and a V driver (14), and timing pulses to be used by the H driver (13U) and the V driver (14) are produced based on timing data produced by a shift register (31U) of the H driver (13U) and a shift register (14A) of the V driver (14). The invention thereby provides a timing generation circuit which can contribute to miniaturization and reduction of the cost of the set and a display apparatus of the active matrix type in which the timing generation circuit is incorporated.

公开(公告)号：NO324000B1

公开(公告)日：2007-07-30

申请号：NO20015907

申请日：2001-12-03

Applicant: SONY CORP

Inventor： NAKAJIMA YOSHIHARU ,  MAEKAWA TOSHIKAZU

IPC: G02F1/133 ,  G09G3/20 ,  G09G20060101 ,  G09G3/30 ,  G09G3/36 ,  H04M1/02 ,  H04M1/73

Abstract: This invention provides a liquid crystal display device having a partial screen display mode, in which a latch control circuit (17) first stores white data or black data as color data of one line to latch circuits (121), (131) at the beginning of an image non-display period and then repeatedly reads out and outputs the color data to respective column lines in a display area (11) until the display period ends, thereby stopping the operation to write data to the latch circuits (121), (131) substantially during the entire image non-display period.

公开(公告)号：DE69808711D1

公开(公告)日：2002-11-21

申请号：DE69808711

申请日：1998-08-28

Applicant: SONY CORP

Inventor： NAKAJIMA YOSHIHARU ,  MAEKAWA TOSHIKAZU

IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36

Abstract: A liquid crystal display device having output buffers (16-1, ..., 16-n) corresponding to column lines (20-1, ..., 20-n), comprises analog switches (18-1, ..., 18-n) provided between output ends of the output buffers (16-1, ..., 16-n) and the column lines (20-1, ..., 20-n) respectively, and a switch controller (19) for on-off controlling the analog switches (18-1, ..., 18-n). A DA converter (15) is provided in the preceding stage of the output buffers (16-1, ..., 16-n), and the switch controller (19) turns off the analog switches (18-1, ..., 18-n) during a DA conversion period of the DA converter (15) or during a precharge period prior to DA conversion, and turns on the analog switches (18-1, ..., 18-n) during a predetermined period other than such periods.

公开(公告)号：NO20021396L

公开(公告)日：2002-05-14

申请号：NO20021396

申请日：2002-03-20

Applicant: SONY CORP

Inventor： KIDA YOSHITOSHI ,  NAKAJIMA YOSHIHARU ,  GOTO NAOSHI ,  MAEKAWA TOSHIKAZU ,  KATAOKA HIDEO

IPC: G02F1/13 ,  G02F1/1362 ,  G09G3/00 ,  G09G3/36 ,  G02F1/1345 ,  G09F9/00

Abstract: A liquid crystal display panel 1, to which an external horizontal drive circuit is connected in a TAB, COG, or other form, capable of performing aging by a substrate alone when image display is possible by connecting the external drive circuit, comprising an active matrix display area 2, a vertical drive circuit 4, and a horizontal aging circuit 5 for supplying signals to a plurality of source lines at one time provided on a substrate 3. Also, a medium- to small-sized active matrix type liquid crystal display apparatus used for a PDA etc. able to be produced at a high quality and a low cost without using a time sharing driving method and provided with a horizontal drive circuit as an external circuit, wherein a vertical drive circuit is formed integrally with a liquid crystal display area on a glass substrate by using low temperature PolySi TFTs, a horizontal drive circuit is connected to a liquid crystal display panel substrate by COG, and output terminals of a driver IC constituting the horizontal drive circuit and source lines Ls are in a one-to-one correspondence.

公开(公告)号：NO20021396A

公开(公告)日：2002-05-14

申请号：NO20021396

申请日：2002-03-20

Applicant: SONY CORP

Inventor： KIDA YOSHITOSHI ,  NAKAJIMA YOSHIHARU ,  GOTO NAOSHI ,  MAEKAWA TOSHIKAZU ,  KATAOKA HIDEO

IPC: G02F1/13 ,  G02F1/1362 ,  G09G3/00 ,  G09G3/36 ,  G02F1/1345 ,  G09F9/00

CPC classification number: G09G3/006 ,  G02F1/13452 ,  G02F1/13454 ,  G02F2001/136254 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2330/12

公开(公告)号：NO20015907L

公开(公告)日：2002-01-31

申请号：NO20015907

申请日：2001-12-03

Applicant: SONY CORP

Inventor： NAKAJIMA YOSHIHARU ,  MAEKAWA TOSHIKAZU

IPC: G02F1/133 ,  G09G20060101 ,  G09G3/20 ,  G09G3/30 ,  G09G3/36 ,  H04M1/02 ,  H04M1/73

Abstract: This invention provides a liquid crystal display device having a partial screen display mode, in which a latch control circuit (17) first stores white data or black data as color data of one line to latch circuits (121), (131) at the beginning of an image non-display period and then repeatedly reads out and outputs the color data to respective column lines in a display area (11) until the display period ends, thereby stopping the operation to write data to the latch circuits (121), (131) substantially during the entire image non-display period.

公开(公告)号：DE69320591D1

公开(公告)日：1998-10-01

申请号：DE69320591

申请日：1993-11-23

Applicant: SONY CORP

Inventor： MAEKAWA TOSHIKAZU ,  HAYASHI YUJI

IPC: G09G3/36 ,  H03K3/356 ,  H03K5/02 ,  H03K19/0185 ,  H03K19/003

Abstract: A level converting circuit for an input clock signal having a relatively low amplitude comprising a level converting circuit for converting the input clock signal to an output clock signal having a relatively high amplitude, the level converting circuit having an input transistor which has a predetermined threshold voltage, and detecting/offsetting circuit for detecting the threshold voltage of the input transistor and adding an offset voltage in response to the detected threshold voltage to the input clock signal and then for providing the offset input clock signal to the level converting circuit. The novel setup performs clock interfacing of a thin-film transistor integrated circuit device represented by an active-matrix liquid crystal display device at a relatively high speed at a low voltage below 3 V for example. This allows to fully cope with a recent trend of ever reducing operating voltage of a CMOS gate array constituting an external timing generator, eliminating necessity for building a pulse amplifier based especially on high dielectric-strength MOS process into the gate array to eventually reduce size of the chip.

公开(公告)号：DE69314507T2

公开(公告)日：1998-05-07

申请号：DE69314507

申请日：1993-01-28

Applicant: SONY CORP

Inventor： MAEKAWA TOSHIKAZU

IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  H04N5/66

Abstract: A horizontal driver circuit comprising a shift register for generating horizontal sampling pulses sequentially; and a fixed pattern eliminating circuit, associated with the shift register, for providing a non-overlap time of the horizontal sampling pulses between an Nth stage and an Mth stage posterior thereto. The Mth stage horizontal sampling pulse has a rise whose phase is the same as that of a fall of the Nth stage horizontal sampling pulse. The fixed pattern eliminating circuit comprises means for controlling the rise of the horizontal sampling pulse of the Mth stage by the fall of the horizontal sampling pulse of the Nth stage. The horizontal driver circuit is applicable to a two-dimensional addressing device and a liquid crystal display device to eliminate a fault of vertical streaks on a displayed image.

公开(公告)号：EP1220018A4

公开(公告)日：2006-08-16

申请号：EP01954377

申请日：2001-07-30

Applicant: SONY CORP

Inventor： KIDA YOSHITOSHI ,  NAKAJIMA YOSHIHARU ,  GOTO NAOSHI ,  MAEKAWA TOSHIKAZU ,  KATAOKA HIDEO

IPC: G02F1/13 ,  G02F1/1362 ,  G09G3/00 ,  G09G3/36

CPC classification number: G09G3/006 ,  G02F1/13452 ,  G02F1/13454 ,  G02F2001/136254 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2330/12

Abstract: A liquid crystal display panel (1) the substrate itself of which can be subjected to aging even if it can display an image by connecting it to an external drive circuit and which is connected to an external drive circuit in the form of TAB or COG comprises, on a substrate (3), an active matrix display area (2), a vertical drive circuit (4), and a horizontal aging circuit (5) for supplying a signal to source lines together. An intermediate- or small-sized high-image quality active matrix liquid crystal display not adopting any time-division drive method, provided with a horizontal drive circuit as an external circuit, manufactured at low cost, and used for a PDA, wherein a vertical drive circuit is fabricated on a glass substrate by use of low-temperature polysilicon TFT integrally with the liquid crystal display area, a horizontal drive circuit is connected to the liquid crystal display panel substrate in the form of COG, and the output terminals of the driver IC constituting the horizontal drive circuit corresponds to source lines (Ls) in a one-to-one relationship.