-
公开(公告)号：DE69808711T2
公开(公告)日：2003-08-14
申请号：DE69808711
申请日：1998-08-28
Applicant: SONY CORP
Inventor： NAKAJIMA YOSHIHARU , MAEKAWA TOSHIKAZU
Abstract: A liquid crystal display device having output buffers (16-1, ..., 16-n) corresponding to column lines (20-1, ..., 20-n), comprises analog switches (18-1, ..., 18-n) provided between output ends of the output buffers (16-1, ..., 16-n) and the column lines (20-1, ..., 20-n) respectively, and a switch controller (19) for on-off controlling the analog switches (18-1, ..., 18-n). A DA converter (15) is provided in the preceding stage of the output buffers (16-1, ..., 16-n), and the switch controller (19) turns off the analog switches (18-1, ..., 18-n) during a DA conversion period of the DA converter (15) or during a precharge period prior to DA conversion, and turns on the analog switches (18-1, ..., 18-n) during a predetermined period other than such periods.
-
公开(公告)号：NO20015907D0
公开(公告)日：2001-12-03
申请号：NO20015907
申请日：2001-12-03
Applicant: SONY CORP
Inventor： NAKAJIMA YOSHIHARU , MAEKAWA TOSHIKAZU
Abstract: This invention provides a liquid crystal display device having a partial screen display mode, in which a latch control circuit (17) first stores white data or black data as color data of one line to latch circuits (121), (131) at the beginning of an image non-display period and then repeatedly reads out and outputs the color data to respective column lines in a display area (11) until the display period ends, thereby stopping the operation to write data to the latch circuits (121), (131) substantially during the entire image non-display period.
-
公开(公告)号：DE69308242D1
公开(公告)日：1997-04-03
申请号：DE69308242
申请日：1993-06-17
Applicant: SONY CORP
Inventor： SUZUKI YOSHIO , NAKAJIMA YOSHIHARU
IPC: G02F1/136 , G02F1/1368 , G02F1/133 , G09G3/36
Abstract: An active matrix liquid crystal display device comprises pixels (LP) composed of a liquid crystal arranged in a matrix and transistors (Tr) for driving the pixels. In a selected period of time, gate pulses (GP) are applied to a gate electrode (G) of each transistor (Tr) for writing video signals in each pixel. Subsequently, in a non-selected period of time, the applying of the gate pulses (GB) is stopped for holding the written video signals. In a transition from the selected period of time to the non-selected period of time, the voltage shift of the video signals can be suppressed by shaping of a fall of the gate pulses smoothly. In place of the above method, the voltage shift of the video signals can be also suppressed by shaping a fall of the gate pulses through dropping the gate pulses after lowering the voltage level of the gate pulses in a specified value once directly before the transition from the selected period of time to the non-selected period of time.
-
公开(公告)号：DK1626486T3
公开(公告)日：2012-02-06
申请号：DK04733188
申请日：2004-05-14
Applicant: SONY CORP
Inventor： NAKAJIMA YOSHIHARU , KIDA YOSHITOSHI
IPC: H02M3/07
-
-
Patent Agency Ranking
公开(公告)号：NO20021396D0
公开(公告)日：2002-03-20
申请号：NO20021396
申请日：2002-03-20
Applicant: SONY CORP
Inventor： KIDA YOSHITOSHI , NAKAJIMA YOSHIHARU , GOTO NAOSHI , MAEKAWA TOSHIKAZU , KATAOKA HIDEO
IPC: G02F1/13 , G02F1/1362 , G09G3/00 , G09G3/36 , G02F
Abstract: A liquid crystal display panel 1, to which an external horizontal drive circuit is connected in a TAB, COG, or other form, capable of performing aging by a substrate alone when image display is possible by connecting the external drive circuit, comprising an active matrix display area 2, a vertical drive circuit 4, and a horizontal aging circuit 5 for supplying signals to a plurality of source lines at one time provided on a substrate 3. Also, a medium- to small-sized active matrix type liquid crystal display apparatus used for a PDA etc. able to be produced at a high quality and a low cost without using a time sharing driving method and provided with a horizontal drive circuit as an external circuit, wherein a vertical drive circuit is formed integrally with a liquid crystal display area on a glass substrate by using low temperature PolySi TFTs, a horizontal drive circuit is connected to a liquid crystal display panel substrate by COG, and output terminals of a driver IC constituting the horizontal drive circuit and source lines Ls are in a one-to-one correspondence.
-
公开(公告)号：NO326879B1
公开(公告)日：2009-03-09
申请号：NO20021396
申请日：2002-03-20
Applicant: SONY CORP
Inventor： NAKAJIMA YOSHIHARU , MAEKAWA TOSHIKAZU , KIDA YOSHITOSHI , GOTO NAOSHI , KATAOKA HIDEO
IPC: G02F1/13 , G02F1/1362 , G09G3/00 , G09G3/36
Abstract: A liquid crystal display panel 1, to which an external horizontal drive circuit is connected in a TAB, COG, or other form, capable of performing aging by a substrate alone when image display is possible by connecting the external drive circuit, comprising an active matrix display area 2, a vertical drive circuit 4, and a horizontal aging circuit 5 for supplying signals to a plurality of source lines at one time provided on a substrate 3. Also, a medium- to small-sized active matrix type liquid crystal display apparatus used for a PDA etc. able to be produced at a high quality and a low cost without using a time sharing driving method and provided with a horizontal drive circuit as an external circuit, wherein a vertical drive circuit is formed integrally with a liquid crystal display area on a glass substrate by using low temperature PolySi TFTs, a horizontal drive circuit is connected to a liquid crystal display panel substrate by COG, and output terminals of a driver IC constituting the horizontal drive circuit and source lines Ls are in a one-to-one correspondence.
-
公开(公告)号：SG136016A1
公开(公告)日：2007-10-29
申请号：SG2006022115
申请日：2003-05-30
Applicant: SONY CORP
Inventor： NAKAJIMA YOSHIHARU , KIDA YOSHITOSHI , MAEKAWA TOSHIKAZU
IPC: G02F1/133 , G09G3/20 , G09G3/30 , G09G3/36 , H03F3/34 , H03F3/50 , H03F3/68 , H03F3/72 , H03M1/74
Abstract: An analog buffer circuit which has small input and output offsets and reduced power consumption even if it is formed on an insulating substrate by TFTs, a display device which uses the analog buffer circuit as a peripheral driving circuit for a display unit, and a portable terminal in which the display device is provided as a screen display unit are provided. By performing offset detection on a source follower in such a manner that, for example, two capacitors Cn1 and Cn2 are connected to the gate of a NMOS transistor Qn11 as a source follower, and conduction/nonconduction control of switches Sn1 to Sn5 are performed, if needed, and by sequentially canceling the detected offsets, a final offset voltage is sufficiently reduced and high precision offset cancellation is realized.
-
公开(公告)号：NO20015907A
公开(公告)日：2002-01-31
申请号：NO20015907
申请日：2001-12-03
Applicant: SONY CORP
Inventor： NAKAJIMA YOSHIHARU , MAEKAWA TOSHIKAZU
CPC classification number: G09G3/3688 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2310/04 , G09G2310/08 , G09G2330/021 , G09G2330/022
-
公开(公告)号：SG67340A1
公开(公告)日：1999-09-21
申请号：SG1996007822
申请日：1996-04-09
Applicant: SONY CORP
Inventor： UCHINO KATSUHIDE , MAEKAWA TOSHIKAZU , NAKAJIMA YOSHIHARU , TSUBOTA HIROYOSHI
Abstract: The invention provide a display apparatus of a plural pixel simultaneous driving system wherein sample and hold noise included in a video signal is removed before the video signal is supplied to a display panel (11). A video signal processing circuit operates in response to a timing signal (P S/H) supplied from an external timing signal source, and delays an input video signal (Vsigin) supplied thereto from an external video signal source to produce an output video signal (V S/H). The video signal processing circuit includes a first sample and hold circuit (3), a second sample and hold circuit (4) and a differential circuit (5). The first sample and hold circuit repetitively samples and holds the input video signal in response to the timing signal. The second sample and hold circuit repetitively samples and holds a predetermined reference signal (Vref) in response to the same timing signal. The differential circuit differentially processes the input video signal after it has been sampled and held and the reference signal after it has been sampled and held to produce an output video signal from which sample and hold noise synchronized with the timing signal has been removed.
-
-
-
-
-
-
-
-
-
Search Results
212
records
(took 0.074 seconds)
