LAYING-OUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

    公开(公告)号:JPH0844780A

    公开(公告)日:1996-02-16

    申请号:JP20135694

    申请日:1994-08-02

    Applicant: SONY CORP

    Abstract: PURPOSE:To provide the laying-out method for the semiconductor integrated circuit which can give large degrees of freedom to the arrangement, wiring, and correction of I/O and reduce the chip area by minimizing the redundant part of wiring between the I/O and other blocks. CONSTITUTION:To design a layout of chip level by using compaction processing, a block A including at least an I/O cell and another block B are separated and made hierarchical on the chip level (steps S11 and S12), terminals on the periphery of the block B are arranged in the arrangement order of the terminals of an internal block connected to the block A (step S13), and final chip size is estimated to calculate optimum values of arrangement coordinates of the I/O cell (steps S14 and S15); and the compaction processing restricted with the optimum values is performed (step S16), then a spacer cell is inserted into this layout (step S17), and the blocks A and B are wired (step S18).

    LAYOUT DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT

    公开(公告)号:JPH0969115A

    公开(公告)日:1997-03-11

    申请号:JP26841995

    申请日:1995-10-17

    Applicant: SONY CORP

    Abstract: PROBLEM TO BE SOLVED: To easily executes a compaction processing without destructing the hierarchical structure by executing inter-hierarchy connection by an inter- hierarchy connection means, removing a redundant wiring from hierarchical cell data(HCD) and then executing the compaction processing of HCD just above unsubstituted HCD for which HCD were substituted just before the processing. SOLUTION: A compaction processing means (a) executes compaction processing for the lowermost HCD, a substituting processing means (b) substitutes the unprocessed HCD for the processed HCD and an inter-hierarchy connection means (d) executes inter-hierarchy connection between the substituted HCD and HCD just above the substituted HCD. A redundant wiring removing means (e) removes a redundant wiring from the HCD and a compaction processing means (f) executes compaction processing for HCD just above the unsub-stituted HCD for which HCD were substituted just before the processing.

    WIRING LAYOUT METHOD
    5.
    发明专利

    公开(公告)号:JPH06342456A

    公开(公告)日:1994-12-13

    申请号:JP15700593

    申请日:1993-06-28

    Applicant: SONY CORP

    Abstract: PURPOSE:To prevent short-circuiting, the spreading of wiring intervals or the generation of disconnection by providing desired several parallel wires as one thick bundled wire and performing wiring layout with this bundled wire as a reference. CONSTITUTION:The signal names of all the desired wires to be bundled are designated but in this column, there are four signal lines A0-A3 and the respective signal lines A0-A3 are called bundled wire BUS 1. Then, the desired several wires to be bundled are provided as one thick wire (bundled wire) BUS 1, the thick bundled wire BUS 1 is divided while wiring the remaining wires, connection with a block terminal is performed, and wiring rules are matched by loading compaction after redundant wires generated by the terminal connection are erased. Namely, when any redundant part is generated at branched wiring such as when the bundled wire BUS 1 is branched or the like, the redundant wire is removed, the connection of wiring is returned to the original connection, automatic connection is performed from the terminals of respective wires to the branched wire, and automatic wiring processing is completed.

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