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公开(公告)号：JP2010124361A
公开(公告)日：2010-06-03
申请号：JP2008297658
申请日：2008-11-21
Inventor： FUKUDA SHINICHI , NIIFUKU YOSHIHIDE
IPC: H04L27/06 , H04B5/02 , H04L25/03 , H04L25/497
Abstract: PROBLEM TO BE SOLVED: To achieve a communication apparatus for accurately analyzing reception information.
SOLUTION: In the communication apparatus configured to execute the detection processing of reception information from a reception signal by radio communication, a detection part inputs reception information superimposed on a carrier signal, and generates a detection signal including the reception information, and a partial response equalization processing part executes signal processing by the partial response equalization processing to the detection signal, inputs a signal corrected by the partial response equalization processing part to the detection part configured of a Viterbi decoder, for example, and obtains the reception information. Thus, it is possible to correct distortion generated in the communication path by the partial response equalization processing part, and to acquire the reception information from the corrected signal. Accordingly, it is possible to accurately transmit information in communication having a high transmission rate.
COPYRIGHT: (C)2010,JPO&INPITAbstract translation: 要解决的问题：实现用于准确分析接收信息的通信装置。 解决方案：在被配置为通过无线电通信从接收信号执行接收信息的检测处理的通信装置中，检测部分输入叠加在载波信号上的接收信息，并产生包括接收信息的检测信号， 部分响应均衡处理部分通过部分响应均衡处理对检测信号执行信号处理，例如将由部分响应均衡处理部分校正的信号输入到由维特比解码器构成的检测部分，并获得接收信息。 因此，可以通过部分响应均衡处理部分校正在通信路径中产生的失真，并且从校正信号获取接收信息。 因此，可以准确地发送具有高传输速率的通信中的信息。 版权所有（C）2010，JPO＆INPIT
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公开(公告)号：JP2008052067A
公开(公告)日：2008-03-06
申请号：JP2006228651
申请日：2006-08-25
Inventor： HAGA SHUICHI , KIRITA SHINA , NIIFUKU YOSHIHIDE
IPC: G02F1/13357 , G02F1/1335
Abstract: PROBLEM TO BE SOLVED: To provide a light source device capable of further improving the color reproducibility of a display device while suppressing the manufacturing cost. SOLUTION: Wavelength selection filters 32 for respective colors are arranged respectively corresponding to LEDs 31B, 31G, 31R for the respective colors. In the wavelength selection filters 32 for the respective colors, monochromatic rays (B color ray, G color ray, R color ray) of corresponding LEDs are transmitted while narrowing their respective spectral widths. Transmission of the B color ray and the R color ray through the color filter 15G for green color resulting in their mixing with the G color ray does not take place any longer, and consequently color purity of display light emitted from an LCD panel 1 is heightened. Furthermore, the LEDs are used as light sources, thereby making its configuration low in cost. COPYRIGHT: (C)2008,JPO&INPIT
Abstract translation: 要解决的问题：提供能够在抑制制造成本的同时进一步提高显示装置的颜色再现性的光源装置。 解决方案：用于各种颜色的波长选择滤光器32分别对应于相应颜色的LED 31B，31G，31R。 在用于各种颜色的波长选择滤光器32中，相应的LED的单色光（B色，G色，R彩色）发射同时使其各自的光谱宽度变窄。 通过彩色滤光片15G透过彩色滤色片15G，使其与G色光混合，不再发生B色光和R色，并且因此从LCD面板1发出的显示光的色纯度提高 。 此外，LED用作光源，从而使其构造成本低。 版权所有（C）2008，JPO＆INPIT
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公开(公告)号：JP2006259585A
公开(公告)日：2006-09-28
申请号：JP2005080135
申请日：2005-03-18
Inventor： HAGA SHUICHI , NAKATSUE TAKEHIRO , MATSUMOTO TATSUHIKO , KUSUKI TSUNEO , IGARASHI TAKAHIRO , NIIFUKU YOSHIHIDE
IPC: G02F1/1335 , G02B5/20 , G02F1/13357
Abstract: PROBLEM TO BE SOLVED: To provide a color liquid crystal display device capable of display with a wide color range. SOLUTION: The color liquid crystal display device 100 comprises a transmission type color display panel 10 with a color filter and a back light source 20, wherein the back light source 20 is equipped with a fluorescent lamp 21 with a wide color reproduction range and the color filter 19 comprises a primary-color color filter transmitting red light, green light, and blue light by wavelength selection and complementary color filters of one or more colors. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 解决的问题：提供能够在宽的色彩范围内显示的彩色液晶显示装置。 彩色液晶显示装置100包括具有滤色器和背光源20的透射型彩色显示面板10，其中背光源20配备有具有宽的色彩再现范围的荧光灯21 并且滤色器19包括通过波长选择发送红光，绿光和蓝光的原色滤色器和一种或多种颜色的互补滤色器。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2000341132A
公开(公告)日：2000-12-08
申请号：JP15129499
申请日：1999-05-31
Applicant: SONY CORP
Inventor： NAKAGAWA TOSHIYUKI , NIIFUKU YOSHIHIDE
Abstract: PROBLEM TO BE SOLVED: To decrease the size of a table and to make the circuit scale smaller although a minimum run and a conversion rate are unchanged by converting an (n)-bit variable-length code into an (m)-bit data sequence in accordance with a conversion table. SOLUTION: With a minimum run d=4 and at a conversion rate m/n=2/5, an (n)-bit variable-length code is converted into an (m)-bit data sequence. A code word from a comparison inverse NRZI conversion part 1 is sectioned by 5 bits and supplied to a restriction length deciding part 11, a substitute code detection part 12 which keep the minimum run, a substitute code detection part 13 which keeps a maximum run and conversion parts 14-1 to 14-4. The conversion parts 14-1 to 14-4 refer to an internal conversion table and covert a supplied code word, when a conversion rule corresponding to the supplied code word is registered and then outputs the converted data sequence to a multiplexer 15. The conversion table has a substitute code which keeps the minimum run, a substitute code for keeping the maximum run, and other basic codes.
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公开(公告)号：JPH11154381A
公开(公告)日：1999-06-08
申请号：JP13192598
申请日：1998-05-14
Applicant: SONY CORP
Inventor： NAKAGAWA TOSHIYUKI , NARAHARA TATSUYA , NIIFUKU YOSHIHIDE
Abstract: PROBLEM TO BE SOLVED: To enable to reproduce a clock stably. SOLUTION: When data (limit code) in which the minimum inversion interval Tmin is continued plural times is included in data inputted from a shift register 11, it is detected by a Tmin continuous limit code detecting section 13. When a detected signal is inputted from the Tmin continuous limit code detecting section 13, a restriction length discriminating section 12 discriminates restriction length (i) as restriction length corresponding to a limit code, and outputs it to a multiplexer 15. The multiplexer 15 selects an output of converter corresponding to restriction length supplied from the restriction length discriminating section 12 out of converters 14-1 to 14-r, and outputs it to a run detection processing section 17 through a buffer 16.
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Patent Agency Ranking
公开(公告)号：JPH11134172A
公开(公告)日：1999-05-21
申请号：JP29728097
申请日：1997-10-29
Applicant: SONY CORP
Inventor： NAKAGAWA TOSHIYUKI , NIIFUKU YOSHIHIDE
Abstract: PROBLEM TO BE SOLVED: To easily reproduce a clock by shortening the largest inverting interval and also to stably demodulate the data despite occurrence of reading errors by attaining the finite transmission of the worst error. SOLUTION: The parameters of variable length codes (d, k; m, n; r) are defined as (1, 6; 2, 3; 5) respectively, and the bit of a prescribed position of a code whose largest run (k) is infinite when those parameters are continuous is defined as an indefinite bit. At the same time, the bit of a prescribed position of a code that has a prescribed number of zeros are continuos from the most significant bit toward the higher order bits, i.e., a code having the sum of the number of zeros and the largest number of zeros continuous from the most significant bit toward the lower order bits of the next code that is larger than the run (k) is also defined as an indefinite bit. Furthermore, a conversion table 13i which selected a code string where ((r/2)×3) bits form no repetitive pattern when the constraint length (r) is an even number is used to convert the m-bit data into an n-bit code.
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公开(公告)号：JPH10125009A
公开(公告)日：1998-05-15
申请号：JP27034096
申请日：1996-10-11
Applicant: SONY CORP
Inventor： NAKAGAWA TOSHIYUKI , INO HIROYUKI , YOSHIMURA SHUNJI , KAI SHINICHI , NIIFUKU YOSHIHIDE , IIDA MICHIHIKO , KAWASHIMA TETSUJI , SATO MASASHI
Abstract: PROBLEM TO BE SOLVED: To improve a bit error rate and secure a skew margin by a method wherein channel bit data are corrected when there is a location which does not meet conditions of the minimum continuous length and the maximum continuous length within the channel bit data obtained by binarizing a signal read out of a recording medium. SOLUTION: By using an n-tuple (n: an integer of 2 of more) clock obtained by making n-tuple a channel clock of reproduced data by a bit clock generating part 2, channel bit data which do not meet conditions of the minimum continuous length d7 of the same symbol are detected by a (d'-1) detection part 4, and a correction position of the channel bit data which have the continuous length (d'-1) of the same symbol is designated by a correction bit position designation part 5, and the channel bit data are corrected so that the minimum continuous length of the same symbol is set to be d' by a data correction part 6.
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公开(公告)号：JPH0620400A
公开(公告)日：1994-01-28
申请号：JP19457792
申请日：1992-06-30
Applicant: SONY CORP
Inventor： NIIFUKU YOSHIHIDE , INO HIROYUKI , CHAGI YASUYUKI , NAKAGAWA TOSHIYUKI
Abstract: PURPOSE:To quickly recover step out by providing a detecting circuit which extracts an edge part of a recorded signal detected with binary and makes it a pulse train, a latch circuit which keeps numbers of channel lock of which inversion intervals are each edge spacing, and a counter, and detecting quickly a synchronizing signal. CONSTITUTION:This device is provided with an edge detecting (NRZI) circuit 2 which extracts a edge part of a recorded signal detected with binary code and makes it a pulse train, and a counter 6 which measures numbers of channel lock T of inversion intervals which are spaces of each edge extracted from the circuit 2. Thereby, when a combination of an inversion interval measured at the time and an inversion interval measured at one interval before is same as a combination of the maximum magnetizing reversal interval Tmax and Tmax-kT (k= 1 or 2), it is judged that a synchronizing signal is detected. Therefore, the synchronizing signal can be quickly detected and step out can be quickly recovered, even when frame structure becomes large.
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公开(公告)号：JPH04313863A
公开(公告)日：1992-11-05
申请号：JP7990391
申请日：1991-04-12
Applicant: SONY CORP
Inventor： CHAGI YASUYUKI , NIIFUKU YOSHIHIDE , INO HIROYUKI
Abstract: PURPOSE:To reproduce a clock signal easily and surely by making different each reference level, providing plural level comparators, synthesizing the output, and supplying the result to the phase comparator of the phase synchronizing loop. CONSTITUTION:The reference voltage of voltage sources 34 and 35 is set to the same size and reverse polarity. Since respective reference levels of three comparators 31, 32 and 33 are made different, the output of respective comparators 31-33 does not simultaneously occur. In a synthesizing circuit 50, respective outputs of the comparators 31-33 pass through two-step EX-OR respectively, and thus, they are synthesized at the same delaying time and the output of the circuit 50 is supplied to a phase comparator 43. In accordance with the fact whether the output of the circuit 50 is fast or slow against the clock from a VCO41, it is supplied from the comparator 43 to the VCO41 and from the VCO41, a repropducing signal phase-synchronized with a ternary input signal is obtained. Thus, the clock signal phase-synchronized with the multi-value input signal is surely reproduced.
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公开(公告)号：JPS63228472A
公开(公告)日：1988-09-22
申请号：JP6202787
申请日：1987-03-17
Applicant: SONY CORP
Inventor： IIJIMA TATSUYA , NIIFUKU YOSHIHIDE , OMORI TAKASHI , SATO TAKASHI , KURODA TOSHIYUKI
IPC: G11B20/12
Abstract: PURPOSE:To convert and record a bit of information based on a first format to a bit of information based on a second format by detecting the changing point of a bit of first sub-code information with a sub-code information generating means for the first sub-code information excluding TOC information and generating a bit of second sub-code information based on a detecting flag. CONSTITUTION:At sub-code information generating sources 2-5, the first sub- code information including TOC (table of contents) information, namely, corresponding to a CD format is generated, processed by a processing means 9 and based on the output signal, the second sub-code information corresponding to a DAT format is generated by a sub-code information generating means 17. Then, the first sub-code information excluding the TOC information detects the changing point and based on the detecting flag, the second sub-code information is generated. The TOC information is converted to the second sub-code information by the processing means 9 and outputted through the sub-code information generating means 17. In a recording means 8, the second sub-code information is recorded together with a bit of main information.
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