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公开(公告)号:JPH0634311B2
公开(公告)日:1994-05-02
申请号:JP10957883
申请日:1983-06-18
Applicant: SONY CORP
Inventor: OOSAWA HIDEKAZU , TANAKA MASATO , YOSHIZAWA MAMORU , NAKAI JUN , KOJIMA JUICHI
IPC: G11B20/18
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公开(公告)号:JPS601666A
公开(公告)日:1985-01-07
申请号:JP10887483
申请日:1983-06-17
Applicant: SONY CORP
Inventor: NAKAI JIYUN , OOSAWA HIDEKAZU , YOSHIZAWA MAMORU
Abstract: PURPOSE:To increase the width of a main track in order to improve the sound quality and to facilitate easy production of a fixed head, by recording alternately the 1st and 2nd data groups containing auxiliary data different in bit rate to a single piece of auxiliary track in time division. CONSTITUTION:The 1st auxiliary signal S-AMS which must be reproduced in both fixed speed and high speed modes is supplied to a generator 9 for the 1st auxiliarty data AMS via a terminal 7. While the 2nd auxiliary signal S-SUB which must be reproduced only in a fixed speed mode is supplied to a generator 11 for the 2nd auxiliary data SUB which is converted in a bit rate shorter than the data AMS via a terminal 8. These obtained data AMS and SUB are encoded by a common encoder 12 and then applied with the digital modulation through a digital modulator 13. The 1st and 2nd auxiliary data groups D-AMS and D-SUB are recorded to an auxiliary track with relationship to a main digital code signal. In this cases, both data groups undergo previously the digital modulation and signal processing. A reproduction system 10B has a reverse signal operation to a record system 10a.
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公开(公告)号:JPH0634299B2
公开(公告)日:1994-05-02
申请号:JP10887583
申请日:1983-06-17
Applicant: SONY CORP
Inventor: NAKAI JUN , OOSAWA HIDEKAZU , YOSHIZAWA MAMORU
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公开(公告)号:JPS601669A
公开(公告)日:1985-01-07
申请号:JP10957783
申请日:1983-06-18
Applicant: SONY CORP
Inventor: OOSAWA HIDEKAZU , TANAKA MASATO , YOSHIZAWA MAMORU , NAKAI JIYUN , KOJIMA YUUICHI
Abstract: PURPOSE:To correct a long burst error by recording plural words of even and odd numbers to the 1st and 2nd track groups respectively which are separated in the width direction of a recording medium and applying coding to each word for error correction. CONSTITUTION:Signal lines 18 led out of the shift registers of a shift register circuit group 12 are switched and supplied to a channel encoder 19. The output of the encoder 19 is amplified and supplied to a recording head 21. Here the symbols of odd words are recorded to eight tracks set at the upper side of the width direction of a magnetic tape through switching of lines 18. At the same time, a parity Q is recorded to a track close to the edge. The recorded data is reproduced and subjected to the error correction and the interleave from a reproduction decoder.
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公开(公告)号:JPS601668A
公开(公告)日:1985-01-07
申请号:JP10887783
申请日:1983-06-17
Applicant: SONY CORP
Inventor: NAKAI JIYUN , OOSAWA HIDEKAZU , YOSHIZAWA MAMORU
IPC: G11B15/087 , G11B20/10 , G11B20/12 , G11B27/22 , G11B27/30
Abstract: PURPOSE:To eliminate the use of an auxiliary track and to reduce the circuit in scale by putting an auxiliary digital code signal into the time series space of a main digital code signal which is applied with time base compression, and recording simultaneously both main and auxiliary digital code signals to the same track. CONSTITUTION:The right and left sound signals SL and SR are digitized and written to a pair of RAM4 and 5 via a switching means 3. These written signals are processed for the data arrangement and are written again to the RAM4 and 5. The main digital code signal MDCS which is applied with time base compression is extracted alternately by a switching means 8 since the read clocks of the RAM4 and 5 are earlier than the write clocks. The prescribed arrangement of data is carried out to the signal sent from an auxiliary digital code signal SDCS generator 1 so that said signal can be put into the space of time series of the signal MDCS. Both signals SDCS and MDCS are switched alternately by a switching means 12 and extracted and applied with phase modulation, then recorded to each prescribed track with relative relationship.
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公开(公告)号:JPS601667A
公开(公告)日:1985-01-07
申请号:JP10887583
申请日:1983-06-17
Applicant: SONY CORP
Inventor: NAKAI JIYUN , OOSAWA HIDEKAZU , YOSHIZAWA MAMORU
Abstract: PURPOSE:To eliminate the mutual interference between the 1st and 2nd auxiliary data and to facilitate the extraction and separation of these data, by selecting a bit frequency so as to separate sufficiently the frequency bands of both auxiliary data with each other then recording these data after applying frequency multiplexing. CONSTITUTION:The 1st and 2nd auxiliary signals S-AMS and S-SUB which must be reproduced in the high speed and fixed speed modes are supplied to a signal converting circuit 30 via terminals 7 and 8 respectively. The circuit 30 converts both signals S-AMS and S-SUB into the prescribed digital codes respectively and selects each bit frequency so as to separate sufficiently the frequencies of both signals with each other. Then these signals are applied with frequency multiplexing to be outputted. These signal outputs are recorded to a signal auxiliary track of a recording tape 5 with relationship to a main digital code signal. While a reproduction system reverses the signal operation of a record system via a signal adversely converting circuit 50.
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公开(公告)号:JPS59158141A
公开(公告)日:1984-09-07
申请号:JP3195483
申请日:1983-02-28
Applicant: Sony Corp
Inventor: OOSAWA HIDEKAZU
IPC: H04L9/06
CPC classification number: H04L9/0625
Abstract: PURPOSE:To secure secrecy among groups on a transmission line at a small frequency of calculation by inputting a system code, and arranging and using plural twod-dimensional small matrixes which are a square matrix corresponding to the number of elements of a plain statement block and exclude a zero matrix on a main diagonal as a key. CONSTITUTION:The transmission line is divided into plural groups, and the system code KS which is common to the same group and different for other groups is employed to perform calculation including it. An input plain statement block (m) is generated from a plain statement and the front inversion of the block (m) is performed to obtain m'. Conversion P is performed to divide it into two, i.e. x1 and x1 . Inferiors indicate the numbers of times of the conversion. Each element is shifted cyclically to left by a specific number of bits for x1 and x1 to perform rotation conversion. Thus, an enciphered statement block which is hardly deciphered is obtained by the conversion. Then, data groups obtained by the conversion are processed by calculation based upon the cipher key K1 and system code KS several times. The resulting data are put together and reconverted into 32-bit two-dimensional data. Then, the reverse conversion of the front inversion T is carried out to obtain an enciphered statement block.
Abstract translation: 目的:通过输入系统代码,以较小的计算频率在传输线上的组之间保密,并且安排和使用多个二维小矩阵,它们是对应于一个简单语句块的元素的数量的正方形矩阵, 排除主对角线上的零矩阵作为关键字。 构成:将传输线分成多个组,并且使用与同一组通用并且对于其他组不同的系统代码KS进行包括它的计算。 从一个简单的语句生成一个输入简单语句块(m),并执行块(m)的正面反转以获得m'。 执行转换P以将其分成两个,即x1 <1和x1 <2>。 未成年人指示转换次数。 每个元素周期性地向左移动一个特定的位数,用于x1 <1和x1 <2来进行旋转转换。 因此,通过转换获得几乎不被解密的加密语句块。 然后,通过基于加密密钥K1和系统代码KS的计算,进行通过转换获得的数据组。 将所得数据放在一起并重新转换为32位二维数据。 然后,进行前向反转T的逆转换,得到加密语句块。
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公开(公告)号:JPS59148086A
公开(公告)日:1984-08-24
申请号:JP2247483
申请日:1983-02-14
Applicant: Sony Corp
Inventor: OOSAWA HIDEKAZU
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公开(公告)号:JPH0463461B2
公开(公告)日:1992-10-09
申请号:JP10887683
申请日:1983-06-17
Applicant: SONY CORP
Inventor: NAKAI JUN , OOSAWA HIDEKAZU , YOSHIZAWA MAMORU
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公开(公告)号:JPS60247866A
公开(公告)日:1985-12-07
申请号:JP10305684
申请日:1984-05-22
Applicant: SONY CORP
Inventor: NAKAI JIYUN , OOSAWA HIDEKAZU
Abstract: PURPOSE:To keep interchangeability by which an n-track mode recording tape can be reproduced in a 2n-track mode, to the recording tape under a condition where hardware is commonly used, and to obtain powerful error correcting ability even in the n-track mode, by providing an encoding means for (2n) tracks and a distributing means which time-division-multiplexes the output of the encoding means to (n) tracks. CONSTITUTION:In order to match 12-bit input data words to the data of 48-kHz sampling rate, 2-channel, and 16-bit quantization which are the original input of an encoding section 30, a 12-16 converter 20 which divides the 12-bit input data words into 16-bit time slots is provided before the encoding section 30. Moreover, since data of 20-track quantity (16 symbols plus 4 inspection symbols) are obtained as the output of the encoding section 30, a distributor 40 for distributing the output to a recording head 50 of 10-track quantity is provided. The distributor 40 is a, for example, buffer memory and performs time division multiplex process which records data to be recorded on two tracks on one track and so forth.
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