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    Differential circuit with improved signal balance
    1.
    发明授权
    Differential circuit with improved signal balance 失效
    差分电路具有改善的信号平衡

    公开(公告)号：US3917991A

    公开(公告)日：1975-11-04

    申请号：US49593074

    申请日：1974-08-08

    Applicant: SONY CORP

    Inventor： OTA YOSHIO ,  TAKEDA MASASHI

    IPC: H03F3/343 ,  G01R19/22 ,  H02M7/12 ,  H02M7/21 ,  H03D1/06 ,  H03D1/18 ,  H03F3/34 ,  H03F3/45 ,  H02M7/00

    CPC classification number: G01R19/22 ,  H03D1/06 ,  H03D1/18

    Abstract: A differential circuit having a first pair of transistors connected in a differential amplifier to amplify an applied signal. Input terminals of a second differential amplifier are connected to output terminals of the first amplifier and a feedback circuit is connected from an output terminal of the second differential amplifier to an input circuit of the first differential amplifier to supply thereto an output signal of the second amplifier in inverse polarity to the signal applied to the first amplifier. This improves the balance of the output signal of the second differential amplifier relative to the zero level, and this output signal may be rectified by a full-wave rectifier to have equal excursions from the zero axis for each successive half cycle of a sinusoidal signal.

    Abstract translation: 差分电路具有连接在差分放大器中的放大应用信号的第一对晶体管。 第二差分放大器的输入端连接到第一放大器的输出端，并且反馈电路从第二差分放大器的输出端连接到第一差分放大器的输入电路，以向第二差分放大器的输出信号提供第二放大器的输出信号 与施加到第一放大器的信号相反极性。 这改善了第二差分放大器相对于零电平的输出信号的平衡，并且该输出信号可以由全波整流器整流，以在正弦信号的每个连续的半周期从零轴起相等的偏移。

    Integrated logic circuit for the decoder of a multi-channel stereo apparatus
    2.
    发明授权
    Integrated logic circuit for the decoder of a multi-channel stereo apparatus 失效
    用于多声道立体声装置的解码器的集成逻辑电路

    公开(公告)号：US3885099A

    公开(公告)日：1975-05-20

    申请号：US41993373

    申请日：1973-11-29

    Applicant: SONY CORP

    Inventor： TSURUSHIMA KATSUAKI ,  OTA YOSHIO ,  TAKEDA MASASHI

    IPC: H03F3/68 ,  H04S3/02 ,  H04R5/00

    CPC classification number: H04S3/02

    Abstract: A logic circuit which is easily and relatively inexpensively produced as an integrated circuit for use with the decoder of a multi-channel stereo apparatus of the type which converts two composite signals LT and RT into four output signals containing dominant signal components LF'',RF'',LB'', respectively, with each of the output signals further including subdominant signal components as crosstalk. The logic circuit includes a plurality of full wave rectifiers for separately rectifying each of the four output signals, a first differential amplifier for producing a signal representative of the difference between the rectified LF'' and RF'' output signals and a second differential amplifier for producing an output signal representative of the difference between the rectified LB'' and RB'' output signals. The difference signal outputs are compared in a third differential amplifier which generates first and second control signals of opposite polarity which are each representative of the difference between the difference signal outputs. These control signals may be employed to control respective gain control amplifiers interposed in four output signals transmitting lines so as to depress the crosstalk.

    Abstract translation: 一种逻辑电路，其容易且相对便宜地生成为用于将两个复合信号LT和RT转换成包含主要信号分量LF'，RF'的四个输出信号的多通道立体声装置的解码器使用的集成电路， ，LB'，其中每个输出信号还包括次优势信号分量作为串扰。 逻辑电路包括多个全波整流器，用于分别对四个输出信号中的每一个进行整流;第一差分放大器，用于产生表示经整流的LF'和RF'输出信号之间的差的信号;以及第二差分放大器，用于产生 输出信号表示整流LB'和RB'输出信号之间的差异。 差分信号输出在产生具有相反极性的第一和第二控制信号的第三差分放大器中进行比较，每个控制信号各自代表差分信号输出之间的差。 可以采用这些控制信号来控制放置在四个输出信号传输线中的各个增益控制放大器，以便抑制串扰。

    GAIN CONTROL CIRCUIT
    3.
    发明专利
    GAIN CONTROL CIRCUIT 未知

    公开(公告)号：CA946054A

    公开(公告)日：1974-04-23

    申请号：CA153866

    申请日：1972-10-13

    Applicant: SONY CORP

    Inventor： WAKU TOSHIHIKO ,  OTA YOSHIO

    IPC: H03F3/34 ,  H03F3/347 ,  H03G3/10 ,  H03G3/30

    Abstract: A gain control circuit having a pair of first and second NPN-type transistors whose emitters are grounded and whose collectors are connected with each other and through a constant current source to a DC source. A third NPN-type transistor has its collector connected to the DC source, its emitter connected to the bases of the first and second transistors through separate resistors and also grounded through a resistor connected in parallel with a capacitor, and its base connected to the collector of the first transistor. A PNP-type transistor has its emitter connected to the base of the first transistor and its collector grounded. An input signal is applied to the base of the first transistor and a control signal is applied to the base of the PNP-type transistor.

    DIFFERENTIAL CIRCUIT WITH IMPROVED SIGNAL BALANCE
    4.
    发明专利
    DIFFERENTIAL CIRCUIT WITH IMPROVED SIGNAL BALANCE 未知

    公开(公告)号：CA1030619A

    公开(公告)日：1978-05-02

    申请号：CA206655

    申请日：1974-08-09

    Applicant: SONY CORP

    Inventor： OTA YOSHIO ,  TAKEDA MASASHI

    IPC: H03F3/343 ,  G01R19/22 ,  H02M7/12 ,  H02M7/21 ,  H03D1/06 ,  H03D1/18 ,  H03F3/34 ,  H03F3/45 ,  H03F3/04

    Abstract: A differential circuit having a first pair of transistors connected in a differential amplifier to amplify an applied signal. Input terminals of a second differential amplifier are connected to output terminals of the first amplifier and a feedback circuit is connected from an output terminal of the second differential amplifier to an input circuit of the first differential amplifier to supply thereto an output signal of the second amplifier in inverse polarity to the signal applied to the first amplifier. This improves the balance of the output signal of the second differential amplifier relative to the zero level, and this output signal may be rectified by a full-wave rectifier to have equal excursions from the zero axis for each successive half cycle of a sinusoidal signal.

    5.
    发明专利
    未知

    公开(公告)号：DE2359862A1

    公开(公告)日：1974-06-12

    申请号：DE2359862

    申请日：1973-11-30

    Applicant: SONY CORP

    Inventor： TSURUSHIMA KATSUAKI ,  OTA YOSHIO ,  TAKEDA MASASHI

    IPC: H03F3/68 ,  H04S3/02 ,  H04R5/04

    Abstract: A logic circuit which is easily and relatively inexpensively produced as an integrated circuit for use with the decoder of a multi-channel stereo apparatus of the type which converts two composite signals LT and RT into four output signals containing dominant signal components LF',RF',LB', respectively, with each of the output signals further including subdominant signal components as crosstalk. The logic circuit includes a plurality of full wave rectifiers for separately rectifying each of the four output signals, a first differential amplifier for producing a signal representative of the difference between the rectified LF' and RF' output signals and a second differential amplifier for producing an output signal representative of the difference between the rectified LB' and RB' output signals. The difference signal outputs are compared in a third differential amplifier which generates first and second control signals of opposite polarity which are each representative of the difference between the difference signal outputs. These control signals may be employed to control respective gain control amplifiers interposed in four output signals transmitting lines so as to depress the crosstalk.

    INTEGRATED LOGIC CIRCUIT FOR THE DECODER OF A MULTI-CHANNEL STEREO APPARATUS
    6.
    发明专利
    INTEGRATED LOGIC CIRCUIT FOR THE DECODER OF A MULTI-CHANNEL STEREO APPARATUS 未知

    公开(公告)号：CA982486A

    公开(公告)日：1976-01-27

    申请号：CA187109

    申请日：1973-11-30

    Applicant: SONY CORP

    Inventor： TSURUSHIMA KATSUAKI ,  OTA YOSHIO ,  TAKEDA MASASHI

    IPC: H03F3/68 ,  H04S3/02

    Abstract: A logic circuit which is easily and relatively inexpensively produced as an integrated circuit for use with the decoder of a multi-channel stereo apparatus of the type which converts two composite signals LT and RT into four output signals containing dominant signal components LF',RF',LB', respectively, with each of the output signals further including subdominant signal components as crosstalk. The logic circuit includes a plurality of full wave rectifiers for separately rectifying each of the four output signals, a first differential amplifier for producing a signal representative of the difference between the rectified LF' and RF' output signals and a second differential amplifier for producing an output signal representative of the difference between the rectified LB' and RB' output signals. The difference signal outputs are compared in a third differential amplifier which generates first and second control signals of opposite polarity which are each representative of the difference between the difference signal outputs. These control signals may be employed to control respective gain control amplifiers interposed in four output signals transmitting lines so as to depress the crosstalk.

    7.
    发明专利
    未知

    公开(公告)号：DE2438473A1

    公开(公告)日：1975-03-06

    申请号：DE2438473

    申请日：1974-08-09

    Applicant: SONY CORP

    Inventor： OTA YOSHIO ,  TAKEDA MASASHI

    IPC: H03F3/343 ,  G01R19/22 ,  H02M7/12 ,  H02M7/21 ,  H03D1/06 ,  H03D1/18 ,  H03F3/34 ,  H03F3/45

    Abstract: A differential circuit having a first pair of transistors connected in a differential amplifier to amplify an applied signal. Input terminals of a second differential amplifier are connected to output terminals of the first amplifier and a feedback circuit is connected from an output terminal of the second differential amplifier to an input circuit of the first differential amplifier to supply thereto an output signal of the second amplifier in inverse polarity to the signal applied to the first amplifier. This improves the balance of the output signal of the second differential amplifier relative to the zero level, and this output signal may be rectified by a full-wave rectifier to have equal excursions from the zero axis for each successive half cycle of a sinusoidal signal.

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