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    Differential circuit with improved signal balance
    1.
    发明授权
    Differential circuit with improved signal balance 失效
    差分电路具有改善的信号平衡

    公开(公告)号：US3917991A

    公开(公告)日：1975-11-04

    申请号：US49593074

    申请日：1974-08-08

    Applicant: SONY CORP

    Inventor： OTA YOSHIO ,  TAKEDA MASASHI

    IPC: H03F3/343 ,  G01R19/22 ,  H02M7/12 ,  H02M7/21 ,  H03D1/06 ,  H03D1/18 ,  H03F3/34 ,  H03F3/45 ,  H02M7/00

    CPC classification number: G01R19/22 ,  H03D1/06 ,  H03D1/18

    Abstract: A differential circuit having a first pair of transistors connected in a differential amplifier to amplify an applied signal. Input terminals of a second differential amplifier are connected to output terminals of the first amplifier and a feedback circuit is connected from an output terminal of the second differential amplifier to an input circuit of the first differential amplifier to supply thereto an output signal of the second amplifier in inverse polarity to the signal applied to the first amplifier. This improves the balance of the output signal of the second differential amplifier relative to the zero level, and this output signal may be rectified by a full-wave rectifier to have equal excursions from the zero axis for each successive half cycle of a sinusoidal signal.

    Abstract translation: 差分电路具有连接在差分放大器中的放大应用信号的第一对晶体管。 第二差分放大器的输入端连接到第一放大器的输出端，并且反馈电路从第二差分放大器的输出端连接到第一差分放大器的输入电路，以向第二差分放大器的输出信号提供第二放大器的输出信号 与施加到第一放大器的信号相反极性。 这改善了第二差分放大器相对于零电平的输出信号的平衡，并且该输出信号可以由全波整流器整流，以在正弦信号的每个连续的半周期从零轴起相等的偏移。

    Automatic gain control circuit
    2.
    发明授权
    Automatic gain control circuit 失效
    自动增益控制电路

    公开(公告)号：US3875521A

    公开(公告)日：1975-04-01

    申请号：US29107272

    申请日：1972-09-21

    Applicant: SONY CORP

    Inventor： KIKUCHI MASAFUMI ,  TAKEDA MASASHI

    IPC: H03G3/30 ,  H03F3/30

    CPC classification number: H03G3/3015

    Abstract: A circuit for controlling the gain of an amplifier to prevent signal clipping even if the power supply voltage drops. The AGC amplifier has one input electrode connected to the output of the main amplifying circuit and a second input electrode connected by a non-linear circuit to one terminal of the power supply to vary the bias on this transistor with changes in the power supply voltage so as to stabilize the operation of the transistor in spite of changes in the amplitude of the audio signal due to the changes in the power supply voltage. The transistor furnishes an AGC signal to control a variable impedance across the input of the amplifier to be controlled. The variation in this impedance reduces the gain of the controlled amplifier when amplifying high signal levels.

    Abstract translation: 用于控制放大器的增益以防止信号削波的电路，即使电源电压下降。 AGC放大器具有连接到主放大电路的输出的一个输入电极和通过非线性电路连接到电源的一个端子的第二输入电极，以随着电源电压的变化来改变该晶体管上的偏置 为了稳定晶体管的操作，尽管由于电源电压的变化引起的音频信号的振幅的变化。 晶体管提供AGC信号以控制待控制的放大器的输入端的可变阻抗。 当放大高信号电平时，该阻抗的变化会降低受控放大器的增益。

    Integrated logic circuit for the decoder of a multi-channel stereo apparatus
    3.
    发明授权
    Integrated logic circuit for the decoder of a multi-channel stereo apparatus 失效
    用于多声道立体声装置的解码器的集成逻辑电路

    公开(公告)号：US3885099A

    公开(公告)日：1975-05-20

    申请号：US41993373

    申请日：1973-11-29

    Applicant: SONY CORP

    Inventor： TSURUSHIMA KATSUAKI ,  OTA YOSHIO ,  TAKEDA MASASHI

    IPC: H03F3/68 ,  H04S3/02 ,  H04R5/00

    CPC classification number: H04S3/02

    Abstract: A logic circuit which is easily and relatively inexpensively produced as an integrated circuit for use with the decoder of a multi-channel stereo apparatus of the type which converts two composite signals LT and RT into four output signals containing dominant signal components LF'',RF'',LB'', respectively, with each of the output signals further including subdominant signal components as crosstalk. The logic circuit includes a plurality of full wave rectifiers for separately rectifying each of the four output signals, a first differential amplifier for producing a signal representative of the difference between the rectified LF'' and RF'' output signals and a second differential amplifier for producing an output signal representative of the difference between the rectified LB'' and RB'' output signals. The difference signal outputs are compared in a third differential amplifier which generates first and second control signals of opposite polarity which are each representative of the difference between the difference signal outputs. These control signals may be employed to control respective gain control amplifiers interposed in four output signals transmitting lines so as to depress the crosstalk.

    Abstract translation: 一种逻辑电路，其容易且相对便宜地生成为用于将两个复合信号LT和RT转换成包含主要信号分量LF'，RF'的四个输出信号的多通道立体声装置的解码器使用的集成电路， ，LB'，其中每个输出信号还包括次优势信号分量作为串扰。 逻辑电路包括多个全波整流器，用于分别对四个输出信号中的每一个进行整流;第一差分放大器，用于产生表示经整流的LF'和RF'输出信号之间的差的信号;以及第二差分放大器，用于产生 输出信号表示整流LB'和RB'输出信号之间的差异。 差分信号输出在产生具有相反极性的第一和第二控制信号的第三差分放大器中进行比较，每个控制信号各自代表差分信号输出之间的差。 可以采用这些控制信号来控制放置在四个输出信号传输线中的各个增益控制放大器，以便抑制串扰。

    SPEECH OUTPUT APPARATUS
    8.
    发明公开
    SPEECH OUTPUT APPARATUS 有权
    语音输出装置

    公开(公告)号：EP1372138A4

    公开(公告)日：2005-08-03

    申请号：EP02707128

    申请日：2002-03-22

    Applicant: SONY CORP

    Inventor： KOBAYASHI ERIKA ,  AKABANE MAKOTO ,  NITTA TOMOAKI ,  KISHI HIDEKI ,  HORINAKA RIKA ,  TAKEDA MASASHI

    IPC: A63H5/00 ,  A63H11/00 ,  G10K15/04 ,  G10L13/00 ,  G10L13/02 ,  G10L13/04 ,  G10L15/00 ,  G10L15/22 ,  G10L13/08

    CPC classification number: G10L13/033 ,  G10L13/00

    Abstract: The present invention relates to a voice output apparatus capable of, in response to a particular stimulus, stopping outputting a voice and outputting a reaction. The voice output apparatus is capable of outputting a voice in a natural manner. A rule-based synthesizer 24 produces a synthesized voice and outputs it. For example, when a synthesized voice "Where is an exit" was produced and outputting of the synthesized voice data has proceeded until "Where is an e" has been output, if a user taps a robot, then a reaction generator 30 determines, by referring to a reaction database 31, that a reaction voice "Ouch!" should be output in response to being tapped. The reaction generator 30 then controls an output controller 27 so as to stop outputting the synthesized voice "Where is an exit?" and output the reaction voice "Ouch!". Thereafter, the reaction generator 30 controls the read pointer of a buffer 26 controlled by the read controller 29 such that the outputting of the synthesized voice is resumed from the point at which the outputting was stopped. Thus, the synthesized voice "Where is an e, Ouch!, xit?" is output.

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