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    ENCODER AND ENCODING METHOD PROVIDING INCREMENTAL REDUNDANCY
    1.
    发明申请
    ENCODER AND ENCODING METHOD PROVIDING INCREMENTAL REDUNDANCY 审中-公开
    提供增量冗余的编码器和编码方法

    公开(公告)号：WO2011104182A3

    公开(公告)日：2011-11-17

    申请号：PCT/EP2011052417

    申请日：2011-02-18

    Applicant: SONY CORP ,  SONY DEUTSCHLAND GMBH ,  MUHAMMAD NABIL ,  STADELMEIER LOTHAR ,  ROBERT JOERG ,  ATUNGSIRI SAMUEL ASANGBENG ,  YAMAMOTO MAKIKO ,  SHINOHARA YUJI ,  SAKAI LUI ,  YOKOKAWA TAKASHI

    Inventor： MUHAMMAD NABIL ,  STADELMEIER LOTHAR ,  ROBERT JOERG ,  ATUNGSIRI SAMUEL ASANGBENG ,  YAMAMOTO MAKIKO ,  SHINOHARA YUJI ,  SAKAI LUI ,  YOKOKAWA TAKASHI

    IPC: H03M13/11 ,  H04L1/00

    CPC classification number: H03M13/11 ,  H03M13/1165 ,  H03M13/3761 ,  H03M13/6519 ,  H04L1/0036 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0059 ,  H04L1/0068 ,  H04L1/0083 ,  H04L2001/0098

    Abstract: The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z1, Z2), comprising: an encoder input (1451) for receiving input data words (D) each comprising a first number K ldpc of information symbols, an encoding means (1452) for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword comprises a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number N ldpc - K ldpc of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number M IR of auxiliary parity symbols, wherein said encoding means (14) is adapted i) for generating said basic codeword portion (B) from an input data word (D) according to a first code, wherein a basic parity symbol is generated by accumulating an information symbol at a parity symbol address determined according to a first address generation rule, and ii) for generating said auxiliary codeword portion (A) from an input data word (D) according to a second code, wherein an auxiliary parity symbol is generated by accumulating an information symbol m at a parity symbol address ?, wherein said parity symbol addresses ? are determined according to a second address generation rule N ldpc - K ldpc + {x + m mod G a x Q IR } mod M IR if x > N ldpc - K ldpc ' wherein x denotes the addresses of a parity symbol accumulator corresponding to the first information symbol of a group of size Ga and Q IR is an auxiliary code rate dependent, predefined constant, and an encoder output (1454) for outputting said codewords (Z1, Z2).

    Abstract translation: 本发明涉及一种用于将输入数据字（D）编码为码字（Z1，Z2）的编码器，包括：编码器输入（1451），用于接收输入数据字（D），每个输入数据字包括第一数目K ldpc 信息符号;编码装置（1452），用于将输入数据字（D）编码为码字（Z1，Z2，Z3，Z4），使得码字包括包含数据部分（D）的基本码字部分（B）;以及 基本奇偶校验码元的第二数量N ldpc -K ldpc的基本奇偶校验部分（Pb）以及包括辅助奇偶校验码元的第三数目M IR的辅助奇偶部分（Pa）的辅助码字部分（A），其中所述 编码装置（14）适于：i）根据第一码从输入数据字（D）产生所述基本码字部分（B），其中通过在确定的奇偶校验符号地址处累积信息符号来产生基本奇偶校验符号 根据第一个地址生成规则，以及ii）用于生成 根据第二代码从输入数据字（D）中除去所述辅助码字部分（A），其中辅助奇偶校验符号通过在奇偶校验符号地址β处累积信息符号m而产生， 根据第二地址生成规则N ldpc -K ldpc + {x + m mod G ax Q IR} mod M IR确定，如果x> N ldpc -K ldpc'，其中x表示与所述第一地址生成规则相对应的奇偶符号累加器的地址 尺寸Ga和Q IR组的第一个信息符号是一个辅助码率相关的预定义常数，和一个用于输出所述码字（Z1，Z2）的编码器输出（1454）。

    Encoder and encoding method providing incremental redundancy
    2.
    发明专利
    Encoder and encoding method providing incremental redundancy 未知

    公开(公告)号：AU2011219954A1

    公开(公告)日：2012-09-13

    申请号：AU2011219954

    申请日：2011-02-18

    Applicant: SONY CORP

    Inventor： LOGHIN NABIL ,  STADELMEIER LOTHAR ,  ROBERT JOERG ,  ATUNGSIRI SAMUEL ASANGBENG ,  YAMAMOTO MAKIKO ,  SHINOHARA YUJI ,  SAKAI LUI ,  YOKOKAWA TAKASHI

    IPC: H03M13/11 ,  H04L1/00

    Abstract: The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z1, Z2), comprising: an encoder input (1451) for receiving input data words (D) each comprising a first number K of information symbols, an encoding means (1452) for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword comprises a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number N - K of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number M of auxiliary parity symbols, wherein said encoding means (14) is adapted i) for generating said basic codeword portion (B) from an input data word (D) according to a first code, wherein a basic parity symbol is generated by accumulating an information symbol at a parity symbol address determined according to a first address generation rule, and ii) for generating said auxiliary codeword portion (A) from an input data word (D) according to a second code, wherein an auxiliary parity symbol is generated by accumulating an information symbol m at a parity symbol address , wherein said parity symbol addresses are determined according to a second address generation rule N - K + {x + mod x } mod if x > N - Kwherein denotes the addresses of a parity symbol accumulator corresponding to the first information symbol of a group of size G and Q is an auxiliary code rate dependent, predefined constant, and an encoder output (1454) for outputting said codewords (Z1, Z2).

    УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ
    3.
    发明专利
    УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ 未知

    公开(公告)号：EA022022B1

    公开(公告)日：2015-10-30

    申请号：EA201070632

    申请日：2008-11-26

    Applicant: SONY CORP

    Inventor： YOKOKAWA TAKASHI ,  YAMAMOTO MAKIKO ,  OKADA SATOSHI ,  SAKAI LUI ,  IKEGAYA RYOJI

    IPC: H03M13/19

    Abstract: Настоящееизобретениекасаетсяустройстваобработкиданныхи способаобработкиданных, которыемогутулучшитьустойчивостьк появлениюошибокв данных. Вдемультиплексоре 25 заменяютв соответствиис правиломсопоставлениябитов LDPC-кодаи битовсимволов, которыепредставляютсимволы, mb битовизбитовкодаи используютбитыкодапослезаменыкакбиты b символов. Согласноправилусопоставления, когдагруппы, вкоторыесгруппированыбитыкодаи битысимволав зависимостиотвероятностипоявленияошибок, используюткакгруппыбитовкодаи группыбитовсимволасоответственно, определяюткомбинациюлюбойгруппыбитовкодаи любойгруппыбитовсимвола, которойдолжнабытьсопоставленагруппабитовкода, иколичествабитовкодаи битовсимвола.

    Data processing device and data processing method
    4.
    发明专利
    Data processing device and data processing method 未知

    公开(公告)号：AU2011304146A1

    公开(公告)日：2013-03-14

    申请号：AU2011304146

    申请日：2011-09-09

    Applicant: SONY CORP

    Inventor： SHINOHARA YUJI ,  YAMAMOTO MAKIKO ,  SAKAI LUI

    IPC: H03M13/19 ,  H04L27/00

    Abstract: The present invention relates to a data processing device and a data processing method capable of improving data error resilience. In a case where LDPC codes having a code length of 4320 bits are mapped to sixteen signal points, a demultiplexer performs replacement assigning b0 to y0, b1 to y4, b2 to y1, b3 to y6, b4 to y2, b5 to y5, b6 to y3 and b7 to y7 for LDPC codes with a code rate of 1/2, and assigning b0 to y0, b1 to y4, b2 to y5, b3 to y2, b4 to y1, b5 to y6, b6 to y3 and b7 to y7 for LDPC codes with code rates of 7/12, 2/3 and 3/4, where (#i+1)-th bits from the most significant bits of 4×2-bit sign bits and of 4×2-bit symbol bits of two successive symbols are represented by bits b#i and y#i, respectively. The present invention can be applied, for example, to a transmission system transmitting LDPC codes.

    DISPOSITIVO DE PROCESAMIENTO DE DATOS Y METODO DE PROCESAMIENTO DE DATOS.
    6.
    发明专利
    DISPOSITIVO DE PROCESAMIENTO DE DATOS Y METODO DE PROCESAMIENTO DE DATOS. 未知

    公开(公告)号：MX2013002697A

    公开(公告)日：2013-08-15

    申请号：MX2013002697

    申请日：2011-09-09

    Applicant: SONY CORP

    Inventor： SHINOHARA YUJI ,  YAMAMOTO MAKIKO ,  SAKAI LUI

    IPC: H03M13/19 ,  H04L27/00

    Abstract: La presente invención se relaciona con un dispositivo de procesamiento de datos y un método de procesamiento de datos capaz de mejorar la resistencia a errores de datos. En un caso donde los códigos de LDPC que tienen una longitud de código de 4,320 bits se mapean en dieciséis puntos de señales, un desmultiplexor realiza reemplazo de asignación b0 a y0, b1 a b4, b2 a y1, b3 a y6, b4 a y2, b5 a y5, b6 a y3, y b7 a y7 para códigos de LDPC con una proporción codificada de 1/2 , y asignación de b0 a y0, b1 a b4, b2 a y5, b3 a y2, b4 a y1, b5 a y6, b6 a y3, y b7 a y7 para códigos de LDPC con proporciones codificadas de 7/12, 3/3 y 3/4, donde(#i+1)-ésimos bits de los bits más significativos de los bits de signo de 4x2bits y de los bits de símbolo de 4x2bits de dos símbolos sucesivos representados por bits de b#i e y#i, respectivamente. La presente invención puede aplicarse, por ejemplo a un sistema de transmisión que transmite códigos de LDPC.

    dispositivo de processamento de dados, e, método de processamento de dados
    9.
    发明专利
    dispositivo de processamento de dados, e, método de processamento de dados 未知

    公开(公告)号：BR112013005712A2

    公开(公告)日：2016-05-10

    申请号：BR112013005712

    申请日：2011-09-09

    Applicant: SONY CORP

    Inventor： SAKAI LUI ,  YAMAMOTO MAKIKO ,  SHINOHARA YUJI

    IPC: H04L27/00 ,  H03M13/19

    Abstract: dispositivo de processamento de dados, e, método de processamento de dados. a presente invenção se refere a um dispositivo de processamento de dados e um método de processamento de dados capaz de melhorar a resiliência de erro de dados. em um caso onde códigos de ldpc tendo um comprimento de código de 4320 bits são mapeados para dezesseis pontos de sinal, um demultiplexador efetua substituição atribuindo b0 à y0, b1 à y4, b2 à y1, b3 à y6, b4 à y2,b5 à y5, b6 à y3 e b7 à y7 para códigos de ldpc com uma taxa de código de 1/2, e atribuindo b0 à y0, b1 à y4, b2 à y5, b3 à y2, b4 à y1, b5 à y6, b6 à y3 e b7 à y7 para código de lpdc com taxa de códigos de 7/12, 2/3 e 3/4, onde (#i+1)-ésimo bits a partir dos mais significativo bit de bits de sinal de 4x2 bits e de bits de símbolo de 4x2 bits de dois sucessivo símbolos são representados pelos bits b#i e y#i, respectivamente. a presente invenção pode ser aplicada, por exemplo, a um sistema de transmissão transmitindo códigos de ldpc.

    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
    10.
    发明专利
    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 未知

    公开(公告)号：CA2809355A1

    公开(公告)日：2012-03-22

    申请号：CA2809355

    申请日：2011-09-09

    Applicant: SONY CORP

    Inventor： SHINOHARA YUJI ,  YAMAMOTO MAKIKO ,  SAKAI LUI

    IPC: H03M13/19 ,  H04L27/00

    Abstract: The present invention relates to a data processing device and a data processing method capable of improving data error resilience. In a case where LDPC codes having a code length of 4320 bits are mapped to sixteen signal points, a demultiplexer performs replacement assigning b0 to y0, b1 to y4, b2 to y1, b3 to y6, b4 to y2, b5 to y5, b6 to y3 and b7 to y7 for LDPC codes with a code rate of 1/2, and assigning b0 to y0, b1 to y4, b2 to y5, b3 to y2, b4 to y1, b5 to y6, b6 to y3 and b7 to y7 for LDPC codes with code rates of 7/12, 2/3 and 3/4, where (#i+1)-th bits from the most significant bits of 4×2-bit sign bits and of 4×2-bit symbol bits of two successive symbols are represented by bits b#i and y#i, respectively. The present invention can be applied, for example, to a transmission system transmitting LDPC codes.

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