公开(公告)号：JP2010103186A

公开(公告)日：2010-05-06

申请号：JP2008271257

申请日：2008-10-21

Applicant: Sony Corp ,  ソニー株式会社

Inventor： TANIGUCHI OSAMU

IPC: H01L33/48

CPC classification number: H01L24/97

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor light emitting apparatus improving both light extraction efficiency and productivity. SOLUTION: In a first wafer 30, a semiconductor light emitting element 10 having bumps 17 and 18 electrically connected to a mesa part 14 and the mesa part 14 is formed on a substrate 40 in a pitch larger than 100 μm. A second wafer 50 has connection electrodes 22 and 23 formed on one surface of a supporting substrate 21 with an area same as or larger than that of the bumps 17 and 18 in the first wafer 30, and via holes 24 and 25 and external electrodes 26 and 27 connected to the connection electrodes 22 and 23 on the other surface of the supporting substrate 21. After laminating the first wafer 30 and the second wafer 50, the substrate 40 of the first wafer 30 is removed, and a region that is not opposed to the semiconductor light emitting element 10 in the second wafer 50 is diced to chip the second wafer 50 and produce a wiring substrate 20. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 解决的问题：提供一种提高光提取效率和生产率的半导体发光装置的制造方法。 解决方案：在第一晶片30中，以大于100μm的间距在基板40上形成具有与台面部分14和台面部分14电连接的凸块17和18的半导体发光元件10。 第二晶片50具有形成在支撑基板21的一个表面上的与第一晶片30中的凸块17和18的面积相同或更大的连接电极22和23，以及通孔24和25以及外部电极26 连接到支撑基板21的另一个表面上的连接电极22和23.在层压第一晶片30和第二晶片50之后，第一晶片30的基板40被移除，并且不相对的区域 切割到第二晶片50中的半导体发光元件10，以对第二晶片50进行芯片切割并生成布线基板20.版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009253022A

公开(公告)日：2009-10-29

申请号：JP2008099242

申请日：2008-04-07

Applicant: Sony Corp ,  ソニー株式会社

Inventor： TANIGUCHI OSAMU ,  SUZUKI NOBUHIRO ,  ONO HIDEKI

IPC: H01L21/331 ,  H01L21/205 ,  H01L21/306 ,  H01L21/338 ,  H01L29/737 ,  H01L29/778 ,  H01L29/812

CPC classification number: H01L29/205 ,  H01L21/02392 ,  H01L21/02463 ,  H01L21/02543 ,  H01L21/30612 ,  H01L29/66318 ,  H01L33/0079 ,  H01L33/02

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which, in the case where an InP-based device is formed with a sacrificial layer in between, is capable of obtaining better device characteristics than those in the case where an AlAs single layer is used as the sacrificial layer, and which avoids the risk that the device layer is etched during etching of the sacrificial layer.
SOLUTION: The method of manufacturing a semiconductor device includes: forming a sacrificial layer 42 which is pseudomorphic to InP after joining or bonding a support substrate 10 to a flat surface 35A of a protection film 35, and then selectively removing it using hydrofluoric acid to separate the InP substrate 41 from the support substrate 10 including an InP-based device layer 21.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造半导体器件的方法，其中在其间形成有牺牲层的基于InP的器件的情况下，能够获得比情况下的牺牲层更好的器件特性 其中使用AlAs单层作为牺牲层，并且避免了在蚀刻牺牲层期间器件层被蚀刻的风险。 解决方案：制造半导体器件的方法包括：在将支撑衬底10接合或接合到保护膜35的平坦表面35A之后，形成与InP伪构的牺牲层42，然后使用氢氟酸选择性地除去 酸以将InP衬底41与包括基于InP的器件层21的支撑衬底10分离。版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2008053250A

公开(公告)日：2008-03-06

申请号：JP2006224845

申请日：2006-08-22

Applicant: Sony Corp ,  ソニー株式会社

Inventor： ONO HIDEKI ,  TANIGUCHI OSAMU

IPC: H01L21/306 ,  H01L21/331 ,  H01L29/737

CPC classification number: H01L21/78 ,  H01L21/6835 ,  H01L23/66 ,  H01L24/19 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L24/91 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/30105 ,  H01L2924/3511 ,  Y10S438/977 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To separate a semiconductor substrate and a supporting substrate (device layer side) surely in a short time in a process for fabricating a semiconductor device employing ELO (expitaxial lift off). SOLUTION: The process for fabricating a semiconductor device comprises a step for separating a semiconductor substrate 1 and a device layer 4 by forming a predetermined device in the device layer 4 which is grown on the semiconductor substrate 1 through a sacrificial layer 2, and then etching the sacrificial layer 2 under a state where a supporting substrate 10 is stuck to the device layer 4. A trench (d) is formed previously from the device layer 4 to the sacrificial layer 2 when the sacrificial layer 2 is removed, and etching liquid is made to permeate up to the sacrificial layer 2 through the trench (d). COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：在制造使用ELO（外延提升）的半导体器件的工艺的过程中，在短时间内可靠地分离半导体衬底和支撑衬底（器件层侧）。 解决方案：制造半导体器件的方法包括通过在半导体衬底1上通过牺牲层2生长的器件层4中形成预定的器件来分离半导体衬底1和器件层4的步骤， 然后在支撑衬底10被粘附到器件层4的状态下蚀刻牺牲层2.当去除牺牲层2时，预先从器件层4到牺牲层2形成沟槽（d），以及 蚀刻液体通过沟槽（d）渗透到牺牲层2。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2006303474A

公开(公告)日：2006-11-02

申请号：JP2006080170

申请日：2006-03-23

Applicant: Sony Corp ,  ソニー株式会社

Inventor： TANIGUCHI OSAMU

IPC: H01L21/331 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide an HBT of which both breakdown strength and high speed are available at high carrier injection (mobility) efficiency, with good reproducibility at a low cost.
SOLUTION: In a hetero junction bipolar transistor (HBT)10, a group III-V compound semiconductor material consisting of an element selected from among Al, Ga, In, As, P and Sb is metamorphically grown on a GaAs substrate 1 to form at least an emitter layer 6, a base layer 5, and a collector layer 4. The base layer 5 is made from GaAs
1-x Sb
x (where, 0 1-y In
y P, where, 0.5

Abstract translation: 要解决的问题：提供在高载流子注入（迁移率）效率下具有击穿强度和高速度的HBT，以低成本具有良好的再现性。 解决方案：在异质结双极晶体管（HBT）10中，由选自Al，Ga，In，As，P和Sb的元素组成的III-V族化合物半导体材料在GaAs衬底1上变质生长 以形成至少一个发射极层6，一个基极层5和一个集电极层4.该基极层5由一个由Sb 1-x Sb Sb S x SB制成（其中， 0 1-y 在 y P中制成，其中0.5

公开(公告)号：JP2004253484A

公开(公告)日：2004-09-09

申请号：JP2003040316

申请日：2003-02-18

Applicant: Sony Corp ,  ソニー株式会社

Inventor： ONO HIDEKI ,  TANIGUCHI OSAMU ,  SUZUKI JUICHI

IPC: H01L21/3065 ,  H01L21/306 ,  H01L21/338 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device in which a T-type gate electrode has a long leg and parasitic capacitance is reduced by providing a wide hollow structure between the head part and the insulation layer on a semiconductor substrate, and to provide a process for fabricating a semiconductor device in which an electrode can be formed with no possibility of short circuit, a T-type gate electrode capable of reducing parasitic capacitance can be formed without increasing the number of fabrication steps, and further scaling-down of element can be realized.
SOLUTION: The semiconductor device 1 comprises the insulation layer 4 formed on the semiconductor substrate 2, and the T-type gate electrode 5 formed on the insulation layer 4 while being connected with the semiconductor substrate 2 through a hole 9 formed in the insulation layer 4. Electrodes 61 and 62 are formed on the semiconductor substrate 2 around the T-type gate electrode 5, the hollow structure 7 is provided between the head part 52 of the T-type gate electrode 5 and the insulation layer 4 in order to isolate the head part 52 of the T-type gate electrode 5 and the electrodes 61 and 62 on the semiconductor substrate 2.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2003209124A

公开(公告)日：2003-07-25

申请号：JP2001382755

申请日：2001-12-17

Applicant: SONY CORP

Inventor： TANIGUCHI OSAMU ,  SUZUKI JUICHI ,  ONO HIDEKI ,  ARAZEKI JUN

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/335 ,  H01L21/338 ,  H01L21/8234 ,  H01L29/20 ,  H01L29/423 ,  H01L29/47 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872 ,  H01L31/0328 ,  H01L31/072

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a field-effect semiconductor device which is capable of reducing parasitic resistance determined by distances between a gate electrode and a source electrode and between the gate electrode and a drain electrode, and is also capable of improving device characteristics and which has superior uniformity and reproducibility, and also to provide a field-effect semiconductor device manufactured by the same. SOLUTION: The method of manufacturing a field-effect semiconductor device comprises a process of forming a gate metal on a semiconductor layer formed of a gallium nitride-based compound semiconductor expressed by a general expression (1) Al x In y Ga 1-x-y N, where x+y=1, 0≤xη1, and 0≤y≤1; and a process of forming the source electrode and the drain electrode self-alignedly with the gate metal as a mask material. A field-effect semiconductor device manufactured by this method is also provided. COPYRIGHT: (C)2003,JPO

公开(公告)号：JPH11195815A

公开(公告)日：1999-07-21

申请号：JP92098

申请日：1998-01-06

Applicant: SONY CORP

Inventor： TSUKAMOTO HIRONORI ,  HINO TOMOKIMI ,  TANIGUCHI OSAMU ,  TODA ATSUSHI ,  MAKINO SAKURAKO

IPC: H01L33/06 ,  H01L33/14 ,  H01L33/28 ,  H01L33/38 ,  H01L33/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element for which the operation life can be extended, by restricting deterioration of electrode while electricity is carried, and also provide its production method, optical recording and/or reproducing equipment using such a semiconductor light-emitting element. SOLUTION: In a semiconductor laser having a plurality of II-VI Group compound semiconductor layer laminated on a substrate, when making a wafer- shaped n-type GaAs substrate 1 where the laser construction has been formed into chips, the n-type GaAs substrate 1 is cleaved together with a plurality of II-VI Group compound semiconductor layers, in such a manner that distance L between the stripe portion and the end face 16 parallel to the strip portion becomes larger than the overall thickness (d) of the laser chip, more desirable larger than 3 times the overall thickness (d) of the laser tip, or practically greater than 400 μm. For example, the overall thickness (d) of the laser chip is set at 600 μm, and at this time, the distance L between the stripe portion and the end face 16 is set at 600 μm.

公开(公告)号：JPH10190154A

公开(公告)日：1998-07-21

申请号：JP28972497

申请日：1997-10-22

Applicant: SONY CORP

Inventor： ISHIBASHI AKIRA ,  TANIGUCHI OSAMU ,  HINO TOMOKIMI ,  KOBAYASHI TAKASHI ,  NAKANO KAZUSHI ,  NAKAYAMA NORIKAZU ,  TODA ATSUSHI ,  TSUKAMOTO HIRONORI ,  MAKINO SAKURAKO

IPC: H01L33/06 ,  H01L33/14 ,  H01L33/28 ,  H01L33/30 ,  H01S5/00 ,  H01S3/18 ,  H01L33/00

Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor light emitting element having excellent characteristics and a long service life, a method for manufactur ing the element, and an optical recording and/or reproducing device using the light element as a light emitting element. SOLUTION: In a semiconductor light emitting element using a II-VI compound semiconductor, at least an active layer 7 is formed to have rugged surfaces and p-type contact layers 11, 12, and 13 are formed to have flat surfaces. The standard deviation of the height of the rugged surfaces of the active layer 7 is adjusted to, for example, about 1-3nm. In addition, the ratio of the intensity of a molecular beam of a group VI element to that of a molecular beam of a group II element is optimized by changing the ratio in accordance with a layer to be grown when clad layers 5 and 9, light guide layers 6 and 8, the active layer 7, the contact layers 11, 12, and 13, etc., are grown manufacturing the semiconductor light emitting element.

公开(公告)号：JPH09232688A

公开(公告)日：1997-09-05

申请号：JP6185696

申请日：1996-02-23

Applicant: SONY CORP

Inventor： TANIGUCHI OSAMU ,  HINO TOMOKIMI ,  OKUYAMA HIROYUKI ,  ISHIBASHI AKIRA

IPC: H01L33/06 ,  H01L33/10 ,  H01L33/12 ,  H01L33/14 ,  H01L33/28 ,  H01L33/30 ,  H01L33/40 ,  H01S5/00 ,  H01S3/18 ,  H01L33/00

Abstract: PROBLEM TO BE SOLVED: To obtain a light emitting element using long life II-VI compound semiconductor in low threshold value current density by successively laminating an active layer of the first conductivity type clad layer, the strain compensation structure single quantum well structure held by barrier layers and the second conductivity type clad layer. SOLUTION: Three kinds of buffer layers, a p-type ZnSe/ZnTeMQW layer and a contact layer wherein a barrier layer made of an n-type ZnMgSSe clad layer, an n-type ZnSSe optical waveguide layer, a strain compensation single quantum well structured active layer, a p-type ZnSSe optical waveguide layer, a p-type ZnSSe clad layer, a p-type ZnSSe layer, a contact layer, a p-type ZnSe and a well layer made of a p-type ZnTe are altenately laminated are successively laminated. With such constitution, in the concrete, within the structure, Zn0.73 Cd0.27 Se layer as the single quantum well layer (light emitting layer) is held by Zn0.81 S0.19 Se layers as the barrier layers.

公开(公告)号：JP2011155061A

公开(公告)日：2011-08-11

申请号：JP2010014339

申请日：2010-01-26

Applicant: Sony Corp ,  ソニー株式会社

Inventor： TANIGUCHI OSAMU

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a thin film transistor that facilitates control of a threshold voltage, and to provide a display device and an electronic apparatus employing the thin film transistor. SOLUTION: The TFT1 includes a gate electrode 13, a gate insulating film 14, an n-type oxide semiconductor layer 15 (channel layer) and source and drain electrodes 17A and 17B on a substrate in this order. A p-type oxide semiconductor layer 16A is laminated and pn-junction is formed on the n-type oxide semiconductor layer 15 at the source and drain electrodes 17A and 17B side. In the n-type oxide semiconductor layer 15, accumulation of carriers is suppressed and thus carrier concentration is reduced. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种便于控制阈值电压的薄膜晶体管，并提供一种采用薄膜晶体管的显示装置和电子装置。 解决方案：TFT1依次包括在基板上的栅电极13，栅极绝缘膜14，n型氧化物半导体层15（沟道层）和源极和漏极电极17A和17B。 层叠p型氧化物半导体层16A，在源电极17A和漏极电极17B侧的n型氧化物半导体层15上形成pn结。 在n型氧化物半导体层15中，载流子的积聚被抑制，因此载流子浓度降低。 版权所有（C）2011，JPO＆INPIT