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    1.
    发明专利
    未知

    公开(公告)号：DE602005016854D1

    公开(公告)日：2009-11-12

    申请号：DE602005016854

    申请日：2005-02-10

    Applicant: SONY CORP

    Inventor： ISHIDA MINORU ,  ARATANI KATSUHISA ,  KOUCHIYAMA AKIRA ,  TSUSHIMA TOMOHITO

    IPC: G11C13/00 ,  G11C13/02 ,  G11C11/56 ,  G11C16/10 ,  G11C16/28 ,  H01L27/10

    Abstract: A memory cell has a structure, in which an inter-electrode material layer is sandwiched between a first electrode and a second electrode. Data is stored by a change in a resistance value between the first electrode and the second electrode. The resistance value when a memory element is in a high resistance state is expressed as R_mem_high; the resistance value when the memory element is in a low resistance state is expressed as R_mem_low1; the resistance value of a load circuit is expressed as R_load; the reading voltage is expressed as Vread by setting the voltage of a second power supply line to the reference voltage; and the threshold voltage is expressed as Vth_critical. In writing data into the memory cell, the low resistance state is created so that these parameters satisfy specific relations. The load circuit is formed by an element having the same structure as of the memory element of the memory cell. The memory cell is therefore arranged such that data reading can be more easily and more precisely performed by setting specific conditions for writing into the memory cell.

    3.
    发明专利
    未知

    公开(公告)号：DE602005011876D1

    公开(公告)日：2009-02-05

    申请号：DE602005011876

    申请日：2005-01-19

    Applicant: SONY CORP

    Inventor： TSUSHIMA TOMOHITO ,  ARATANI KATSUHISA ,  KOUCHIYAMA AKIRA

    IPC: G11C11/15 ,  G11C11/56 ,  G11C8/00 ,  G11C13/02 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10

    Abstract: A memory device is provided in which recording of multi-valued data can be performed at a high speed and the recording of multi-valued data can be performed with a drive circuit having comparatively simple configuration. The memory device is formed of a memory cell including a memory element which stores information according to a state of electric resistance and a MIS transistor as a load connected in series to the memory element. When an operation to change the memory cell from a state of high resistance value to a state of low resistance value is defined as writing and when an operation to change the memory cell from the state of low resistance value to the state of high resistance value is defined as erasing respectively, a resistance value of the memory element after writing is set to a plurality of different levels by controlling gate voltages VG1, VG2 and VG3, which are applied to the MIS transistor at the time of writing, so that different information is respectively assigned to each of the plurality of levels and to the state of high resistance value after erasing to store information of three values or more respectively into a memory element of each memory cell.

    Nonvolatile semiconductor memory device
    6.
    发明专利
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：JP2011165297A

    公开(公告)日：2011-08-25

    申请号：JP2010030528

    申请日：2010-02-15

    Applicant: Sony Corp ,  ソニー株式会社

    Inventor： KITAGAWA MAKOTO ,  SHIIMOTO TSUNENORI ,  TSUSHIMA TOMOHITO

    IPC: G11C13/00 ,  H01L27/10 ,  H01L45/00 ,  H01L49/00

    CPC classification number: G11C13/004 ,  G11C7/1048 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0061 ,  G11C2013/0054

    Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device that achieves high-speed reading with satisfactory accuracy. SOLUTION: A sense amplifier 7A compares a potential of a bit line BL to which a variable cell resistance Rcell is connected, with a reference potential VREF to read a logic of information. A dynamic sensing operation and a static sensing operation can be changed over. In the dynamic sensing operation, a sense node SN is precharged to a precharge voltage VR, and read out by a voltage difference between the precharge voltage VR and a voltage of a plate line PL. In the static sensing operation, the reading is carried out while a current load IRef is connected to the sense node SN. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供以令人满意的精度实现高速读取的非易失性半导体存储器件。 解决方案：读出放大器7A将连接有可变单元电阻Rcell的位线BL的电位与参考电位VREF进行比较，以读取信息逻辑。 可以改变动态感测操作和静态感测操作。 在动态感测操作中，感测节点SN被预充电到预充电电压VR，并且通过预充电电压VR与板线PL的电压之间的电压差读出。 在静态感测操作中，当电流负载IRef连接到感测节点SN时进行读取。 版权所有（C）2011，JPO＆INPIT

    Storage device and information re-recording method
    7.
    发明专利
    Storage device and information re-recording method 审中-公开
    存储设备和信息再记录方法

    公开(公告)号：JP2009146478A

    公开(公告)日：2009-07-02

    申请号：JP2007320578

    申请日：2007-12-12

    Applicant: Sony Corp ,  ソニー株式会社

    Inventor： SHIIMOTO TSUNENORI ,  TSUSHIMA TOMOHITO ,  YASUDA SHUICHIRO

    IPC: G11C13/00 ,  H01L27/10 ,  H01L45/00 ,  H01L49/00

    CPC classification number: G11C13/0007 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2213/56 ,  G11C2213/79 ,  G11C2213/82

    Abstract: PROBLEM TO BE SOLVED: To provide a storage device wherein voltage requiring control is reduced and a peripheral circuit scale is reduced. SOLUTION: A first pulse voltage (VBLR) is supplied to an electrode 11 of a variable resistance element 10 from a first power supply 21 through a bit line (BLR), a second pulse voltage (VWL) for cell selection is supplied to a control terminal 20c of a transistor 20 from a second power supply. 22 through a word line (WL), and a third pulse voltage (VBLT) is supplied to a second input/output terminal 20b of the transistor 20 from a third power supply 23 through the bit line BLT. When rewriting information, cell voltage and a cell current can be varied (reduced or increased) by adjusting the voltage VBLT of the third power supply 23 by the adjusting circuit 24. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种存储装置，其中需要降低电压的电压降低并且外围电路规模减小。 解决方案：通过位线（BLR）将第一脉冲电压（VBLR）从第一电源21提供给可变电阻元件10的电极11，提供用于电池选择的第二脉冲电压（VWL） 连接到来自第二电源的晶体管20的控制端子20c。 22，通过位线BLT从第三电源23向第二输入/输出端子20b提供第三脉冲电压（VBLT）。 当通过调整电路24调节第三电源23的电压VBLT时，可以改变信息，电池电压和电池电流可以变化（减小或增加）。版权所有：（C）2009，JPO＆INPIT

    Variable resistor element, and memory device
    8.
    发明专利
    Variable resistor element, and memory device 有权
    可变电阻元件和存储器件

    公开(公告)号：JP2009071105A

    公开(公告)日：2009-04-02

    申请号：JP2007239011

    申请日：2007-09-14

    Applicant: Sony Corp ,  ソニー株式会社

    Inventor： SHIIMOTO TSUNENORI ,  YASUDA SHUICHIRO ,  SASAKI SATOSHI ,  ARAYA KATSUHISA ,  TSUSHIMA TOMOHITO

    IPC: H01L27/10 ,  H01L45/00 ,  H01L49/00

    Abstract: PROBLEM TO BE SOLVED: To provide a variable resistor element which can get rid of an increase of an erase time even if increasing an area to increase the rewritable number of time.
    SOLUTION: The variable resistor element includes electrodes 11, 14 opposed each other and a variable resistor layer which is formed at least in the opposed region of electrodes 11, 14 and its resistance value changes corresponding to the direction of electric field produced between the electrodes 11, 14 by applying a voltage to electrodes 11, 14. The electrodes 11, 14 have a shape different from a perfect circle or a square. When deforming the opposed portion of the electrodes 11, 14 to a perfect circle or a square which has an area same as the area of the opposed portion of the electrodes 11, 14. The electrodes have a shape and size so that a difference between an upper limit value and lower limit value of inside strength distribution of the electric field produced in the opposed region of electrodes 11, 14 is smaller than a difference between an upper limit value and lower limit value of inside strength distribution of the electric field produced in the deformed opposed region of its two electrodes.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种可变电阻器元件，其可以消除擦除时间的增加，即使增加面积以增加可重写的时间数量。 解决方案：可变电阻器元件包括彼此相对的电极11,14和至少形成在电极11,14的相对区域中的可变电阻层，并且其电阻值对应于电场方向 电极11,14通过向电极11,14施加电压。电极11,14具有不同于正圆或正方形的形状。 当将电极11,14的相对部分变形成具有与电极11,14的相对部分的面积相同的正圆或正方形时，电极的形状和尺寸使得 在电极11,14的相对区域产生的电场的内部强度分布的上限值和下限值小于在电极11,14中产生的电场的内部强度分布的上限值和下限值之间的差 其两个电极的变形相对区域。 版权所有（C）2009，JPO＆INPIT

    Storage element
    9.
    发明专利
    Storage element 有权
    存储元素

    公开(公告)号：JP2006040946A

    公开(公告)日：2006-02-09

    申请号：JP2004214603

    申请日：2004-07-22

    Applicant: Sony Corp ,  ソニー株式会社

    Inventor： ARAYA KATSUHISA ,  TSUSHIMA TOMOHITO ,  NARISAWA KOSUKE ,  OTSUKA WATARU ,  YATSUNO HIDEO

    IPC: H01L27/10

    CPC classification number: G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149 ,  H01L45/1675

    Abstract: PROBLEM TO BE SOLVED: To provide a storage element of a structure which can easily be manufactured with high density. SOLUTION: Recording layers 2 and 3 are installed between two electrodes 1 and 4, and potentials different in polarity are applied to the two electrodes 1 and 4. Thus, a memory cell is composed of resistance change elements 10 where resistance values of the recording layers 2 and 3 reversibly change. In a plurality of adjacent memory cells, the storage elements where at least a part of the layers 2 and 3 constituting the recording layers of the resistance change elements 10 is formed by the same layer in common is constituted. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供可以容易地以高密度制造的结构的存储元件。 解决方案：记录层2和3安装在两个电极1和4之间，并且极性不同的电位施加到两个电极1和4上。因此，存储单元由电阻变化元件10组成，其电阻值 记录层2和3可逆地改变。 在多个相邻的存储单元中，构成了构成电阻变化元件10的记录层的层2和3的至少一部分的存储元件由相同的共同层构成。 版权所有（C）2006，JPO＆NCIPI

    Storage device
    10.
    发明专利
    Storage device 有权
    储存设备

    公开(公告)号：JP2005235360A

    公开(公告)日：2005-09-02

    申请号：JP2004124543

    申请日：2004-04-20

    Applicant: Sony Corp ,  ソニー株式会社

    Inventor： TSUSHIMA TOMOHITO ,  ARAYA KATSUHISA ,  KOCHIYAMA AKIRA

    IPC: G11C11/15 ,  G11C8/00 ,  G11C11/56 ,  G11C13/02 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10

    CPC classification number: G11C11/5685 ,  G11C11/5614 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

    Abstract: PROBLEM TO BE SOLVED: To provide a storage device that can record multiple-value data at high speed, and can record the multiple-value data by a drive circuit having a comparatively simple constitution. SOLUTION: In a constitution of the storage device, a memory cell is formed to have a storage element that stores/holds data depending on a state of electric resistance, and a MIS transistor that is connected in series to the storage element and thus formed as load. When operation of changing the storage element from a high resistance-value state to a low resistance-value state is defined as writing, and operation of changing the element from the low resistance-value state to the high resistance-value state is defined as erasing respectively, gate voltage VG1, VG2 and VG3 applied to the MIS transistor are controlled in writing, and thereby a resistance value of the storage element after writing is set to multiple, different levels; and these multiple levels and a high resistance-value state after erasing are assigned with different information respectively, and thereby information of at least three values can be stored into the storage element of each memory cell. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种可以高速记录多值数据的存储装置，并且可以通过具有相对简单结构的驱动电路记录多值数据。 解决方案：在存储装置的结构中，存储单元形成为具有根据电阻状态存储/保存数据的存储元件和与存储元件串联连接的MIS晶体管， 从而形成为负载。 当将存储元件从高电阻值状态改变为低电阻值状态的操作被定义为写入时，将元件从低电阻值状态改变为高电阻值状态的操作被定义为擦除 分别控制施加到MIS晶体管的栅极电压VG1，VG2和VG3，写入后存储元件的电阻值被设定为多个不同的电平; 并且这些多个电平和擦除后的高电阻值状态分别被分配有不同的信息，从而可以将至少三个值的信息存储到每个存储单元的存储元件中。 版权所有（C）2005，JPO＆NCIPI

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