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公开(公告)号：JPH1198471A
公开(公告)日：1999-04-09
申请号：JP25200697
申请日：1997-09-17
Applicant: SONY CORP
Inventor： YAMAGATA YUTAKA
Abstract: PROBLEM TO BE SOLVED: To prevent mis-decision by applying valid/invalid decision processing stably to identification information and control information on the occurrence of signal deterioration. SOLUTION: The decision circuit is provided with a validity decision circuit group 11 that applies decision processing of validity/invalidity of a prescribed element of an identification control signal respectively separately and with a decision result processing circuit 12 that decides validity/invalidity of the entire identification control signal totally. When the element of all the identification control signal that is a decision object is valid, it is decided that the entire identification control signal is valid and in the case that an element decided invalid is in existence among elements of all the identification control signal that are decision objects, a valid item number N is detected based on decision information (j1-jn) of the validity decision circuit group 11 and various processing is conducted in a form with a hysteresis characteristic and the entire identification control signal is invalidated after the element is decided clearly invalid to prevent mis-decision at signal deterioration.
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公开(公告)号：JPH08181881A
公开(公告)日：1996-07-12
申请号：JP31741894
申请日：1994-12-21
Applicant: SONY CORP
Inventor： YAMAGATA YUTAKA , KORI TERUHIKO , ONIKI ARIYOSHI
Abstract: PURPOSE: To always and accurately count the scanning line number by prohibiting the input of a horizontal synchronizing signal by outputting a mask signal in a required block corresponding to the output of a counter making a round in one H period and generating an interpolation pulse when no horizontal synchronizing signal is inputted after the elapse of one H period. CONSTITUTION: A synchronous pulse synchronizing with the horizontal synchronizing signal is generated by a synchronizing separator circuit 1 and an edge detection circuit 2, and the counter 5 making a round in one H period counts a clock. In the required block in which a noise is generated based on a count value, a first AND circuit 4 is closed by the output of a mask signal generation circuit 6, and the input of the synchronous pulse to the count 5 is prohibited. When no synchronous pulse is inputted even after the elapse of one H period, an interpolation pulse generation circuit 7 is enabled, and a line counter steps by the interpolation pulse. By employing such constitution, the horizontal scanning line number can always and accurately be counted without being affected by the noise and even when a signal is a discontinuous video signal.
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公开(公告)号：JPH05236494A
公开(公告)日：1993-09-10
申请号：JP6932692
申请日：1992-02-20
Applicant: SONY CORP
Inventor： YAMAGATA YUTAKA , SENUMA TOSHITAKA
Abstract: PURPOSE:To correct the level. variance of demodulation output due to jitter of an output signal in the circuit which demodulates a carrier chrominance signal based on the output signal of a digital VCO. CONSTITUTION:The carrier chrominance signal inputted to a color signal input terminal 1 is demodulated in a demodulating circuit 2 by a reference signal (b) for demodulation generated by a sine wave generating circuit 6 based on an output (d) of a digital VCO 9 locked to a burst signal (a) separated by a burst separating circuit 5. A signal f' which is generated by a saw tooth wave generating circuit 10 and corresponds to jitter is used to eliminate the level variance, which occurs in an output (g) of the demodulating circuit 2 based on jitter of the digital VCO 9, by a hue correcting circuit. Consequently, the level variance based on jitter of the digital VCO 9 is eliminated in the output of the hue correcting circuit. The output f' of the saw tooth wave generating circuit 10 may be used to correct the phase of the reference signal (b) for demodulation.
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公开(公告)号：JPH04351008A
公开(公告)日：1992-12-04
申请号：JP15389791
申请日：1991-05-28
Applicant: SONY CORP
Inventor： YAMADA TAKAAKI , YAMAGATA YUTAKA
Abstract: PURPOSE:To vary an output in a smaller phase chip than a phase pitch corresponding to a clock frequency. CONSTITUTION:A PLL in which a VCO is adopted for a ring oscillator 1 is formed and an output tap among output taps (1)-(15) of the said ring oscillator 1 is selected repetitively to rotate the phase, then a frequency of a signal Vp extracted from the said ring oscillator 1 is changed minutely to obtain the output Vp in a far smaller phase pitch than the oscillation period of the ring oscillator 1.
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5.发明专利Display image correcting device, image display device, and display image correction method 有权显示图像校正装置，图像显示装置和显示图像校正方法
公开(公告)号：JP2007122013A
公开(公告)日：2007-05-17
申请号：JP2006196669
申请日：2006-07-19
Inventor： YAMAGATA YUTAKA , SHIROCHI YOSHIKI , FUCHIGAMI TOSHINARI , SHIRAHAMA AKIRA
CPC classification number: H04N17/04 , G09G3/20 , G09G3/2044 , G09G3/2059 , G09G3/3406 , G09G2320/0233 , G09G2320/0285 , G09G2320/0673 , G09G2320/0693
Abstract: PROBLEM TO BE SOLVED: To correct brightness unevenness of a display device more efficiently. SOLUTION: The display image correcting device forms a reference correction amount table, on the basis of a set of reference two-dimensional correction amount data obtained at a correction point, corresponding to the horizontal direction and the vertical direction of an image. This reference correction amount table is defined as only one made to correspond to one specific level of luminance, without preparing two or more tables made to correspond to two or more levels of luminance. In actual correction, three-dimensional correction amount data are obtained, by making the reference two-dimensional correction amount data read out of the specific luminance proportional linearly or non-linearly to the luminance level of the video signal to be corrected. Then, the video signal is corrected by using these three-dimensional correction amount data. COPYRIGHT: (C)2007,JPO&INPIT
Abstract translation: 要解决的问题：更有效地校正显示装置的亮度不均匀性。 解决方案：显示图像校正装置基于在与图像的水平方向和垂直方向相对应的校正点获得的一组参考二维校正量数据，形成基准校正量表。 该参考校正量表仅被定义为对应于一个特定亮度级别的参考校正量表，而不需要准备两个或更多个对应于两个或更多个亮度级别的表。 在实际校正中，通过使从特定亮度读出的参考二维校正量数据与要校正的视频信号的亮度级别线性或非线性成比例地获得三维校正量数据。 然后，通过使用这些三维校正量数据来校正视频信号。 版权所有（C）2007，JPO＆INPIT
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Patent Agency Ranking
公开(公告)号：JPH1198423A
公开(公告)日：1999-04-09
申请号：JP25554897
申请日：1997-09-19
Applicant: SONY CORP
Inventor： YAMAGATA YUTAKA
Abstract: PROBLEM TO BE SOLVED: To obtain a display device whose screen image is not unpleasant even when the presence of a caption is mis-detected by discriminating the screen image is a standard image or a laterally long image, setting the display mode depending on the shape of the screen image, setting an aspect ratio and the display device in response to the display mode and providing an image not causing black stripes to an upper part of the image in the laterally long image display mode. SOLUTION: An infrared ray signal is fed to a controller 3 from a remote commander 19 via a light receiving section 18 and a display mode is set. A television receiver is provided with a wide screen image discrimination circuit 10. The wide screen image discrimination circuit 10 discriminates whether a received video signal is a standard image screen signal or a wide image screen signal, and in the case of the wide screen image, the circuit 10 discriminates whether or not the screen image is with/without a caption. A discrimination signal from the wide screen image discrimination circuit 10 is fed to the controller 3, which decides the display mode. A setting signal for the display mode is fed to an image screen setting circuit 13 or a deflection circuit 16, by which an aspect ratio and a display position are set.
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公开(公告)号：JPH05327349A
公开(公告)日：1993-12-10
申请号：JP15445892
申请日：1992-05-20
Applicant: SONY CORP
Inventor： YAMAGATA YUTAKA , SUGAWARA HIROSHI , WAKAMORI MIKIO , KIYONO SHIZUHIRO
Abstract: PURPOSE:To provide an oscillation circuit which can reduce characteristic fluctuation with temperature changes and can stabilize the oscillation frequency or the output amplitude. CONSTITUTION:In the oscillation circuit where a coil (or a piezoelectric resonator 5) is connected between the input and output terminals of an inverter 1 and further first and second capacitors 6 and 7 are respectively connected between the input and output terminals of the inverter 1 and the ground, the capacity ratio between the first and second capacitors 6 and 7 is changed. Thus, the fluctuation of the oscillation frequency caused by output conductance g0 to be changed as the characteristic of an amplifier circuit 2 is reduced.
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公开(公告)号：JP2007179836A
公开(公告)日：2007-07-12
申请号：JP2005376009
申请日：2005-12-27
Inventor： YAMAGATA YUTAKA
IPC: H01R13/641 , H01R13/66
Abstract: PROBLEM TO BE SOLVED: To obtain a connector and a display device capable of detecting a fitting failure of a plug and a plug seat of a connector.
SOLUTION: A light receiving element 29 is arranged and installed either at a plug 19 or at the plug seat 18 of connectors 5a, 5b of a lamp 6 for a high voltage of an LCD backlight device 31. An alarm and a display are issued, or a high voltage generating circuit are driven and controlled by detecting light in discharge generated by the fitting failure when mutually fitting the main contactors 13, 20 of the plug 19 and the plug seat 18 by the light receiving element 29.
COPYRIGHT: (C)2007,JPO&INPITAbstract translation: 要解决的问题：获得能够检测连接器的插头和插头座的嵌合故障的连接器和显示装置。 解决方案：光接收元件29布置并安装在用于LCD背光装置31的高电压的灯6的连接器5a，5b的插头19或插头座18处。报警器和显示器 或者当通过光接收元件29相互配合插头19和插头座18的主接触器13,20时，通过检测由配合故障产生的放电中的光来驱动和控制高压发生电路。
版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JPH09200643A
公开(公告)日：1997-07-31
申请号：JP2304796
申请日：1996-01-17
Applicant: SONY CORP
Inventor： YAMAGATA YUTAKA , WATANABE KENJI
IPC: H04N5/46
Abstract: PROBLEM TO BE SOLVED: To prevent the malfunction of laterally long image discrimination. SOLUTION: The average luminance of video signals forming the upper and lower sections (black band sections) in the image of inputted video signals is found by an upper/lower average luminance operating part 9b, and the difference between the average luminance calculated here and the luminance of video signals corresponding to the black zone of image is calculated by an upper/lower luminance difference operating part 9c. Further, whether the ratio of area, in which this luminance difference is more than a prescribed level, is higher than a prescribed value or not is discriminated by a big luminance difference detecting part 9d and when it is discriminated the ratio of the area having luminance difference more than the prescribed level is higher than the prescribed value, it is judged that the video signal of 4:3 is inputted to a laterally long image discriminating part 9a. Besides, luminance difference between the average luminance and the luminance of video signals forming the central part of image is calculated by a central part luminance difference operating part 9e and whether the ratio of area, in which this luminance difference is less than a prescribed level, is higher than a prescribed value or not is discriminated by a small luminance difference detecting part 9f. When it is judged the luminance difference is less than a prescribed ratio, the discriminating operation of the laterally long image discriminating part 9a is stopped.
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公开(公告)号：JPH09154037A
公开(公告)日：1997-06-10
申请号：JP30939495
申请日：1995-11-28
Applicant: SONY CORP
Inventor： YAMAGATA YUTAKA , INOUE MASARU , URUSHIBARA MINORU , MIYAZAKI SHINICHIRO , NAITO HIDEFUMI
Abstract: PROBLEM TO BE SOLVED: To form a phase locked loop (PLL) in a digital circuit. SOLUTION: A synchronizing signal extracted from a video signal is gated by an AND gate 3 through a separator circuit 1, and the gated synchronizing signal is supplied to a phase comparator circuit 4. This compared output is inputted through a loop filter 5 to an oscillation circuit 6 composed of a counter and this oscillated output is inputted to the phase comparator circuit 4, so that the PLL can be formed. Further a mask signal generating circuit 10 generates that mask signal from the output of this oscillation circuit 6 and a counter 13 counts how many times the synchronizing signals are continuously absent during the period of this mask signal. When this number of times exceeds a prescribed value, the synchronizing signal from the video signal is extracted and corresponding to this signal, the counter consisting of the oscillation circuit is reset. Thus, the stable and speedy PLL and synchronizing separator circuit are constituted.
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