公开(公告)号：JPH04370556A

公开(公告)日：1992-12-22

申请号：JP17465391

申请日：1991-06-19

Applicant: SONY CORP

Inventor： SATO KOICHI ,  MIURA YUTAKA ,  YASUDA TAKUYA

IPC: G11B15/14

Abstract: PURPOSE:To promote the accuracy of a control signal to be outputted by storing output timing of a control data and an output data in a memory and reading and outputting the output data before outputting the control data. CONSTITUTION:The output data OD is stored in a control pulse generating memory 10 before starting reproducing the VTR 1 by a control circuit 9. That is, when it is detected that a drum is not rotated at a prescribed revolving speed, a pulse generating circuit is stopped, and also the value of a switching pulse error counter is set to zero by the circuit 9. The last output data LOD is stored at 00-04 in the memory 10 by the circuit 9. Then, write starting position specifying information MIR is set at 05, and a timing data TD1 and an output data OD1 are written at 05-09. Then, the data TD1 and OD1 are stored as the last timing data LTD and the last output data LOD. All of the data are processed and stored in the memory, and the data LTD and LOD are outputted via latch circuits 3 and 5 to a latch circuit 6.

公开(公告)号：JP2002207530A

公开(公告)日：2002-07-26

申请号：JP2001002660

申请日：2001-01-10

Applicant: SONY CORP

Inventor： YAMAZAKI MAMORU ,  OGAWA KANJI ,  YASUDA TAKUYA ,  KATSUMOTO TORU ,  TAKAMURA YASUHIRO ,  IDOMOTO YASUTAKA

IPC: G06F1/32 ,  G06F1/04 ,  G06F1/10

Abstract: PROBLEM TO BE SOLVED: To provide a clock supply circuit capable of changing a clock frequency according to a processing mode or an interrupt without causing a delay time following program processing. SOLUTION: In the clock supply circuit, correspondence between a frequency mode and a processing mode of a CPU 20 is stored in a storage circuit 103. When the processing mode or the interrupt of the CPU 20 is detected in a frequency mode setting circuit 101, the frequency mode correspondent to the detected processing mode or interrupt is retrieved from the storage circuit 103, and a clock signal CLK of a prescribed frequency according to the retrieved frequency mode is generated in a clock generation circuit 102. Accordingly, a time from detection of a change of the processing mode and the interrupt in the frequency mode setting circuit 101 to generation of the clock signal CLK in the clock generation circuit 102 is unconnected to a processing speed of a program controlling the CPU 20 and is decided according to a response time of a hardware in the clock supply circuit.