公开(公告)号：CA2448826A1

公开(公告)日：2002-12-05

申请号：CA2448826

申请日：2002-05-24

Applicant: SONY CORP

Inventor： YAMASHITA KEI ,  KAWAGUCHI DAISUKE ,  IKEDA KAZUYUKI ,  YOSHIKAWA MUNEHIRO ,  YOSHIDA HIDEKI ,  ONISHI MANABU ,  MAEDA SATORU

IPC: H04L29/06 ,  H04N5/38 ,  H04N5/44 ,  H04L12/66 ,  H04M11/06 ,  H04N7/08 ,  H04L12/54

Abstract: A transmission/reception apparatus enabling a high-speed processing and a hi gh extensibility when performing a communication protocol processing. In the transmission/reception apparatus transmitting/receiving data according to a predetermined communication protocol, the communication protocol processing is constituted so as to be able to be executed by both of hardware (a first and a second communication protocol processor) and software (a first and a second controller). Thus, for example, the data whose processing load is heavy is processed at a high speed by executing a communication protocol processing b y hardware and the data whose processing load is light is processed by softwar e having a high extensibility. That is, hardware and software are used dependi ng on the data type.

公开(公告)号：DE69315731T2

公开(公告)日：1998-07-16

申请号：DE69315731

申请日：1993-03-24

Applicant: SUMITOMO ELECTRIC INDUSTRIES ,  SONY CORP

Inventor： MURAKAMI DAISUKE ,  KIBAYASHI KENJI ,  MATSUMOTO ISAO ,  YOSHIDA HIDEKI ,  NISHIE MITSUAKI ,  TAKAHASHI SATOSHI ,  UESAKA KATSUMI

IPC: H03F3/08 ,  H03K3/2897 ,  H03K5/08 ,  H04B10/07 ,  H04B10/2507 ,  H04B10/40 ,  H04B10/50 ,  H04B10/60 ,  H04B10/67 ,  H04B10/69

Abstract: A signal detecting apparatus is to obtain hysteresis characteristic at a constant ratio regardless of signal amplitude fluctuations by supplying the threshold level adjusting signal corresponding to the input signal amplitude to the comparison circuit. The threshold value setting signal and the hysteresis adjusting signal is supplied to a comparison circuit through an amplifier and a hysteresis adjusting means having the identical characteristic with the peak hold circuit to set a threshold value and a hysteresis range. Therefore even in the case where the operating characteristic of the amplifier and the peak hold circuit for detecting the peak level of signal amplitude fluctuate, the threshold value and the hysteresis range fluctuation corresponding to the fluctuation. As a result, there can not need the adjustment for resetting the operating characteristic, the threshold value and the hysteresis range in each circuit and thus the time and labor required for adjustment can be further saved.

公开(公告)号：EP1392032A4

公开(公告)日：2005-11-09

申请号：EP02728134

申请日：2002-05-24

Applicant: SONY CORP

Inventor： MAEDA SATORU ,  YOSHIDA HIDEKI ,  ONISHI MANABU ,  YAMASHITA KEI ,  IKEDA KAZUYUKI ,  KAWAGUCHI DAISUKE ,  YOSHIKAWA MUNEHIRO

IPC: H04L29/06 ,  H04N5/38 ,  H04N5/44

CPC classification number: H04N5/4401 ,  H04L29/06 ,  H04L69/08 ,  H04L69/18 ,  H04N5/38 ,  H04N7/163 ,  H04N21/4126 ,  H04N21/42676 ,  H04N21/43615 ,  H04N21/43637 ,  H04N21/4782 ,  H04N21/4786 ,  H04N21/482

Abstract: A transmission/reception apparatus enabling a high-speed processing and a high extensibility when performing a communication protocol processing. In the transmission/reception apparatus transmitting/receiving data according to a predetermined communication protocol, the communication protocol processing is constituted so as to be able to be executed by both of hardware (a first and a second communication protocol processor) and software (a first and a second controller). Thus, for example, the data whose processing load is heavy is processed at a high speed by executing a communication protocol processing by hardware and the data whose processing load is light is processed by software having a high extensibility. That is, hardware and software are used depending on the data type.

公开(公告)号：EP1359748A4

公开(公告)日：2005-06-01

申请号：EP01999110

申请日：2001-11-28

Applicant: SONY CORP

Inventor： YOSHIDA HIDEKI ,  SATO JIN ,  IKEDA KAZUYUKI ,  NORIZUKI TAKASHI ,  SAKUSABE KENICHI ,  KAWAGUCHI DAISUKE ,  YOSHIKAWA MUNEHIRO

IPC: H04B14/04 ,  H04L7/00 ,  H04L13/08 ,  H04N5/04 ,  H04N5/38 ,  H04N5/44 ,  H04N19/00 ,  H04N19/102 ,  H04N19/15 ,  H04N19/152 ,  H04N19/196 ,  H04N19/423 ,  H04N19/44 ,  H04N19/70 ,  H04N7/24

CPC classification number: H04N21/4307 ,  H04N5/04 ,  H04N5/38 ,  H04N5/4401 ,  H04N21/23406 ,  H04N21/44004 ,  H04N21/478

Abstract: A data processor which realizes an AV data transmitting/receiving system of a lower cost. A reception buffer monitor circuit (21) monitors the quantity of received data stored in a reception buffer (6). When a stored data quantity increases above the upper threshold value, the circuit (21) sets the frequency of a reception clock generated by a reception clock generating circuit (8) at a higher frequency. When the stored quantity decreases below the lower reference value, the reception clock frequency is set at a lower frequency. An AV decoder (7) decodes AV data supplied from the reception buffer (6) on the basis of a reception clock supplied from the reception clock generating circuit (8). This invention is applied for a television transmitting/receiving system which transmits and receives television broadcasting signals.

公开(公告)号：CA2430161C

公开(公告)日：2007-05-01

申请号：CA2430161

申请日：2001-11-28

Applicant: SONY CORP

Inventor： IKEDA KAZUYUKI ,  SAKUSABE KENICHI ,  NORIZUKI TAKASHI ,  YOSHIDA HIDEKI ,  SATO JIN ,  KAWAGUCHI DAISUKE ,  YOSHIKAWA MUNEHIRO

IPC: H04B14/04 ,  H04L7/00 ,  H04L13/08 ,  H04N5/04 ,  H04N5/38 ,  H04N5/44 ,  H04N19/00 ,  H04N19/102 ,  H04N19/15 ,  H04N19/152 ,  H04N19/196 ,  H04N19/423 ,  H04N19/44 ,  H04N19/70

Abstract: A data processing apparatus constituting a low-cost audio/video data transmission and reception system is disclosed. A reception buffer monitoring circuit 21 monitors the size of receiver data being accumulated in a reception buffer 6. When the size of accumulated data is found to become higher than a high threshold, the circuit 21 causes a reception clock generation circuit 8 to generate a reception clock with a higher frequency. When the accumulated data size becomes lower than a low threshold, the reception clock is generated with a lower frequency. Based on the reception clock fed from the reception clock generation circuit 8, an audio/video decoder 7 decodes the audio/video data coming from the reception buffer 6. This invention applies advantageously to a television transmission and reception system for transmitting and receiving TV broadcast signals.

公开(公告)号：CA2430161A1

公开(公告)日：2002-06-06

申请号：CA2430161

申请日：2001-11-28

Applicant: SONY CORP

Inventor： SAKUSABE KENICHI ,  KAWAGUCHI DAISUKE ,  YOSHIKAWA MUNEHIRO ,  NORIZUKI TAKASHI ,  YOSHIDA HIDEKI ,  SATO JIN ,  IKEDA KAZUYUKI

IPC: H04B14/04 ,  H04L7/00 ,  H04L13/08 ,  H04N5/04 ,  H04N5/38 ,  H04N5/44 ,  H04N19/00 ,  H04N19/102 ,  H04N19/15 ,  H04N19/152 ,  H04N19/196 ,  H04N19/423 ,  H04N19/44 ,  H04N19/70

Abstract: A data processor which realizes an AV data transmitting/receiving system of a lower cost. A reception buffer monitor circuit (21) monitors the quantity of received data stored in a reception buffer (6). When a stored data quantity increases above the upper threshold value, the circuit (21) sets the frequen cy of a reception clock generated by a reception clock generating circuit (8) a t a higher frequency. When the stored quantity decreases below the lower reference value, the reception clock frequency is set at a lower frequency. An AV decoder (7) decodes AV data supplied from the reception buffer (6) on the basis of a reception clock supplied from the reception clock generating circuit (8). This invention is applied for a television transmitting/receivi ng system which transmits and receives television broadcasting signals.

公开(公告)号：DE69315731D1

公开(公告)日：1998-01-29

申请号：DE69315731

申请日：1993-03-24

Applicant: SUMITOMO ELECTRIC INDUSTRIES ,  SONY CORP

Inventor： MURAKAMI DAISUKE ,  KIBAYASHI KENJI ,  MATSUMOTO ISAO ,  YOSHIDA HIDEKI ,  NISHIE MITSUAKI ,  TAKAHASHI SATOSHI ,  UESAKA KATSUMI

IPC: H03F3/08 ,  H03K3/2897 ,  H03K5/08 ,  H04B10/07 ,  H04B10/2507 ,  H04B10/40 ,  H04B10/50 ,  H04B10/60 ,  H04B10/67 ,  H04B10/69

Abstract: A signal detecting apparatus is to obtain hysteresis characteristic at a constant ratio regardless of signal amplitude fluctuations by supplying the threshold level adjusting signal corresponding to the input signal amplitude to the comparison circuit. The threshold value setting signal and the hysteresis adjusting signal is supplied to a comparison circuit through an amplifier and a hysteresis adjusting means having the identical characteristic with the peak hold circuit to set a threshold value and a hysteresis range. Therefore even in the case where the operating characteristic of the amplifier and the peak hold circuit for detecting the peak level of signal amplitude fluctuate, the threshold value and the hysteresis range fluctuation corresponding to the fluctuation. As a result, there can not need the adjustment for resetting the operating characteristic, the threshold value and the hysteresis range in each circuit and thus the time and labor required for adjustment can be further saved.

公开(公告)号：JP2007013520A

公开(公告)日：2007-01-18

申请号：JP2005191163

申请日：2005-06-30

Applicant: Sony Corp ,  ソニー株式会社

Inventor： TAKAHASHI KEN ,  MUTO TAKAYASU ,  YOSHIDA HIDEKI ,  YAMAMOTO TAKEHIRO ,  NAKAYAMA YOICHI ,  HATA NOBORU ,  ITO ATSUSHI ,  SAITO KENICHI ,  UEDA SATOSHI ,  SAWADA KEISUKE ,  OSHIMA SATORU

IPC: H04L12/951 ,  H04L12/801 ,  H04L12/911

Abstract: PROBLEM TO BE SOLVED: To provide a communication equipment and a communication system for acquiring through-put characteristics and latency characteristics necessary for a system. SOLUTION: This communication equipment is provided with an interface 106 for aggregating a plurality of input packets into one packet, and for outputting them in a batch, and the interface 106 aggregates the input packets based on the dynamically specifiable number of packets, and when the input packets are interrupted during aggregation, the interface 106 aggregates the already inputted packets after the lapse of a dynamically specifiable time-out time. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通信设备和用于获取系统所需的通过特性和延迟特性的通信系统。 解决方案：该通信设备设置有用于将多个输入分组聚合成一个分组并且用于批量输出的接口106，并且接口106基于动态指定数量的分组来聚合输入分组， 并且当在聚合期间输入分组被中断时，接口106在经过可动态指定的超时时间之后聚合已经输入的分组。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004180127A

公开(公告)日：2004-06-24

申请号：JP2002345902

申请日：2002-11-28

Applicant: Sony Corp ,  ソニー株式会社

Inventor： UEDA SATOSHI ,  YOSHIDA HIDEKI

IPC: H04L12/885 ,  H04L12/70 ,  H04L12/56

CPC classification number: H04L47/2416 ,  H04L47/10 ,  H04L47/28

Abstract: PROBLEM TO BE SOLVED: To maintain streaming quality without depending upon the state of a host side control part. SOLUTION: When information data for transmission is inputted from an encoder 310, the RTP transmission processing part 110 of an RTP processing circuit 100 is started to packetize a transport stream. A generated RTP packet is transmitted by using a network device 330. At this time, sender information about transmission is generated and stored. When the RTP packet is received from the network device 330, the RTP reception processing part 120 of the RTP processing circuit 100 depacketizes the RTP packet and outputs a reproduced transport stream to a decoder 320. At this time, recipient information about reception is generated and stored. An RTCP processing means 210 acquires the sender information and recipient information via an internal bus 220, generates an RTCP packet and transmits the RTCP packet from the network device 330. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004165886A

公开(公告)日：2004-06-10

申请号：JP2002328086

申请日：2002-11-12

Applicant: Sony Corp ,  ソニー株式会社

Inventor： USUI SHINJI ,  YOSHIDA HIDEKI ,  KOMAGATA JUNICHI ,  UEDA SATOSHI

IPC: H04L29/14

Abstract: PROBLEM TO BE SOLVED: To verify the state of a communication device or a network in real time.
SOLUTION: In the communication device 1, a control means 10 actuates a communication test processing part 20 when a communication test is started. Test data for the test are generated by a transmission processing part 22. At the transmission processing part 22, a transmission data generating means 27 generates transmission data according to an instruction code stored in a transmission instruction storage means 26. A transmission control means 28 transmits the generated transmission data in specified transmission timing. At a reception processing part 21 of the communication test processing part 20, a verifying means 24 is immediately actuated when reception data are inputted from an input/output means 30. The verifying means 24 uses time information generated by the timer means 23 to obtain time information indicating the point of time when the reception data are inputted and verifies the reception data. The result of the verification by the verifying means 24 is written to a storage means 25 readable from the control means 10.
COPYRIGHT: (C)2004,JPO